Demultiplexing of Address and Data Bus in 8085

Demultiplexing of Address and Data Bus in 8085 – For economic use of pins of the microprocessor 8085, the lower order address bus is multiplexed with the data bus.

This is known as a multiplexed Address/Data Bus (AD0 – AD7). the microprocessor 8085 provides an address during the earlier part of the execution of an instruction on the multiplexed bus (AD0 – AD7).

Data is also available on the same bus during the later part of the execution of an instruction. However, for proper memory or input/output operation, the microprocessor requires the lower-order address and data separately.

The address latch enable (ALE) signal is used to demultiplex the address/data bus. The below figure shows the schematic of demultiplexing of address/data bus (AD0-AD7) using a latch IC (74LS373). The multiplexed address/data bus (AD0-AD7) is connected as the input to the 8-bit latch IC (74LS373). The enable input (G) of the latch IC is connected to the ALE pin of the microprocessor, whereas the output control (OC) pin is grounded.

The abovementioned figure shows the schematic of the demultiplexing of the Address/Data bus using a latch IC (74LS373).

Memory organization in the 8085 microprocessor

ALE signal goes high during the earlier part of the execution of the instruction, the latch is transparent, and AD0-AD7 is reflected as A0-A7. In this way, the complete address is available in the address bus (A0-A15).

Once the address is located, the ALE signal goes low, and the latch is disabled. Now, data may be available on this multiplexed bus (AD0-AD7), which may flow from microprocessor to memory (or I/O) or vice versa.