TRANSLATION LOOK-ASIDE BUFFER in Operating Systems | OS Tutorials

In an operating system, to overcome the problem occur in paging (delay), most virtual memory schemes make use of a special high-speed cache for page table entries, usually called a translation look-aside buffer (TLB). This cache functions in the same way as a memory cache and contains those page table entries that have been most recently used. Figure 1 shows the organization of the resulting paging hardware.

Working with Translation Look Aside Buffer

• Given a virtual address, the processor will first examine the TLB. If the desired page table entry is present (we call it TLB hit), then the frame number is retrieved and the real/physical address is formed.
• However, if the desired page table entry is not found (i.e., TLB miss), then the processor uses the page number to index the process page table and examine the corresponding page table entry.
• If the “present bit” is set, then the page is in main memory, and the processor can retrieve the frame number from the page table entry to form the physical address.
• The processor also updates the TLB to include this new page table entry.
• If the “present bit, is not set“, then the desired page is not in main memory and a memory access fault, called a page fault is issued.

The percentage of times that a page number is found in the associative registers (TLB registers) is called hit ratio.

• For example for 80% hit ratio, if process takes 20 nano-second to search the TLB and 100 nano-second to access memory, then a mapped memory access takes 120 nanoseconds (if page is found in TLB).
• However, if the page is not found in TLB (20 nano-second), then we must first access memory for the page table and frame number (100 nano-second) and then access the desired byte in memory (100 nano-second), for a total of 220 nanoseconds.
• Hence, effective memory access time is calculated by taking its probability.
  • Effective access time = 0.80 x 120 + 0.20 x 220 = 140 nanosecond
  • We observe that, we suffer 40 percent slowdown in memory access time (from 100 to 140 nanosecond).
• If we consider 98% hit ratio, then
  • Effective access time = 0.98 x 120 + 0.02 x 220 = 122 nanosecond

Conclusion

• If a computer system takes ‘t₁‘ time to access TLB and ‘t₂‘ time to access memory then mapped memory access will take t₁ + t₂ time when page number is present in TLB.
• When page number is not present in TLB then we require ‘t₁‘ time to access TLB in which page number is not present and ‘t₁‘ time to access the page number in page table and then ‘t₂‘ time to access memory.
• Hence we require total of t₁ + t’₁ + t₂ time when page number is not present in TLB.
• Hence, effective access can be calculated as: T_eff = Hit ratio x (t₁ + t₂) + Miss ratio x (t₁ + t’₁ + t₂).

Flowchart Showing the Use of TLB

The flowchart shown in figure 2, shows that if the derived page is not in main memory a page fault interrupt causes the page fault handling routines to be invoked.