Some of the semiconductor chips are needed to connect peripherals to the system bus. these chips are called interfacing devices. all peripherals and memory share the same bus, however, the microprocessor communicates with only one peripheral at a time. for the proper functioning of this system, tri-state logic devices are necessary.
Types of Interfacing Logic Devices
- Tri-State Devices
- Buffer
- Encoder
- Decoder
- Latch
Tri-State Devices
As the name suggests, the tri-state devices have three states: logic 1, logic 0, and high impedance. A tri-state logic device is shown in the below image. A tri-state logic device has three terminals:
- input
- output
- enable
When the third line (enable line) is activated. the tri-state logic functions the same way as ordinary logic devices. when the third line is deactivated, the device behaves as disconnected from the system, this is named a high impedance state.
(a) Active high enable line
| Enable | Input | Output |
|---|---|---|
| 1 | 0 | 0 |
| 1 | 1 | 1 |
| 0 | * | High Impedance |
(b) Active low enable line
| Enable | Input | Output |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | * | High Impedance |
The tri-state logic device with active-low enables line behaves just opposite to the device discussed above. the tri-state logic device is critical to the proper functioning of the microprocessor-based system.
Buffer
Whenever a system is designed, a number of devices are connected to the output of one digital device. if the output current of the digital device is not sufficient to drive other devices, the current capacity of the output of the digital device has to increase. the buffer is used to increase the driving capability of a digital or logic device. it is also known as the driver. a buffer increases the output current.
Sometimes, a change in voltage levels is required. this is also achieved by a suitable buffer or driver. a buffer is symbolized by a triangle as shown in the below image. for an inverting buffer, a bubble is put at the output point of the triangle. a tri-state buffer has one additional line named enable. when enable line is low (for active low case), the circuit behaves as a buffer, otherwise, it stays in the high impedance state.
In microprocessor-based systems, the buffer is used to increase the driving capability of the data and address bus. since the address bus is unidirectional, a unidirectional buffer (example – 74LS244) is used however data bus s bidirectional, a bidirectional buffer (example – 74LS245) is used.
(a) Buffer
| Input | Output |
|---|---|
| 0 | 0 |
| 1 | 1 |
(b) Inverting Buffer
| Input | Output |
|---|---|
| 0 | 1 |
| 1 | 0 |
(c) tristate buffer (active low)
| Enable | Input | Output |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | * | High Impedance |
There are various buffer driver ICs are available. some of them are shown in the below table.
| IC Number | Description |
|---|---|
| 7406, 7416 | Hex inverter buffer/driver with open collector output |
| 7407, 7417 | Hex Buffer/driver with open collector output |
| 74125 | Quad bus buffers gates with 3 state outputs; output is enabled when c = ‘0’ |
| 74126 | Quad bus buffers gates with 3 state outputs; output is enabled when c=’1′ |
| 74240 | Octal buffers/line drivers/line receivers, inverted 3 state outputs |
| 74241, 74244 | Octal buffers/line drivers/line receivers, inverted 3 state outputs |
| 74245 | Octal bus buffer/driver (Bidirectional) noninverted 3 state outputs |
| 7426, 7437 | Quad 2 input NAND buffers |
| 7438 | Quad 2 input NAND buffers with open collector outputs |
| 7440 | Dual 4 input NAND buffers |
| 7428 | Quad 2 input NOR Buffers |
| 7433 | Quad 2 input NOR buffers with open collector output |
| 74128 | Quad 2 input NOR line drivers |
Encoder
The encoder is a logic circuit that provides the appropriate code as the output for each input signal. the examples of encoder ICs are:
- 74LS147 decimal to BCD encoder
- 74LS148 octal to binary encoder
The hexadecimal to binary encoder can be realized using two 74LS148 ICs and a data selector. the IC 74LS148 is also known as a priority encoder. it has eight inputs and one active low enable signal. it has five output signals (three are encoding lines and two are output enable indicators). when the encoder is enabled and one line, for example, line 3 goes low, the output 011. if two or more input signals are activated simultaneously it ignores the low priority inputs and encodes the highest priority input. the output of this encoder (IC 74LS148) is active low means output will be inverted. when input line 3 is active the output is 100 instead of 011.
| Input | Output | ||
|---|---|---|---|
| E1 | I7 I6 I5 I4 I3 I2 I1 I0 | O2 O1 O0 | G2 E0 |
| 1 | x x x x x x x x | 1 1 1 | 1 1 |
| 0 | 1 1 1 1 1 1 1 1 | 1 1 1 | 1 0 |
| 0 | 1 1 1 1 1 1 1 0 | 0 0 0 | 1 0 |
| 0 | 1 1 1 1 1 1 0 1 | 0 0 1 | 0 1 |
| 0 | 1 1 1 1 1 0 1 1 | 0 1 0 | 0 1 |
| 0 | 1 1 1 1 0 1 1 1 | 0 1 1 | 0 1 |
| 0 | 1 1 1 0 1 1 1 1 | 1 0 0 | 0 1 |
| 0 | 1 1 1 0 1 1 1 1 | 1 0 0 | 0 1 |
| 0 | 1 1 0 1 1 1 1 1 | 1 0 1 | 0 1 |
| 0 | 1 0 1 1 1 1 1 1 | 1 1 0 | 0 1 |
| 0 | 0 1 1 1 1 1 1 1 | 1 1 1 | 0 1 |
Decoder
The microprocessor-based system or any other digital system uses binary numbers for its operations. these understand only the information composed of 0s and 1s, whereas the user is allowed to use decimal numbers. the decoder is used to decode the information from binary to decimal. the decoder is a logic circuit that identifies each combination of the signals present at the input. the decoding is the reverse process of encoding. examples of decoders are BCD to decimal decoder, BCD to segment decoder. the logic diagram of the IC 74LS138 is shown below image.
| Input | Output | |
|---|---|---|
| G2 G1 | I2 I1 I0 | O7 O6 O5 O4 O3 O2 O1 O0 |
| 1 x | x x x | 1 1 1 1 1 1 1 1 |
| x 0 | x x x | 1 1 1 1 1 1 1 1 |
| 0 1 | 0 0 0 | 1 1 1 1 1 1 1 0 |
| 0 1 | 0 0 1 | 1 1 1 1 1 1 0 1 |
| 0 1 | 0 1 0 | 1 1 1 1 1 0 1 1 |
| 0 1 | 0 1 1 | 1 1 1 1 0 1 1 1 |
| 0 1 | 1 0 0 | 1 1 1 0 1 1 1 1 |
| 0 1 | 1 0 1 | 1 1 0 1 1 1 1 1 |
| 0 1 | 1 1 0 | 1 0 1 1 1 1 1 1 |
| 0 1 | 1 1 1 | 0 1 1 1 1 1 1 1 |
Latch
A flip-flop is the basic memory unit. a flip-flop in its simplest form is called a latch. it is a 1-bit memory element. it stores logic ‘0’ or logic ‘1’. the latch is used as a temporary storage device. for the temporary storage of n bits, an n-bit latch is composed of a number of 1-bit latches, then the n-bits of a binary word are transferred to the latch in parallel.
Also, read
A latch is used commonly to interface output devices. a typical example of a latch is the 74LS75 D-flip-flop. this is actually a level trigged D-flip-flop. in this latch, when the enable signal (E) is high. the latch behaves as transparent. the output follows the input signal at pin D. when the enable signal goes low, the latch stores the input data at the last moment. this data is continuously available at the output termination (Q) of the latch till the enable signal is low. Once the enable signal is high, the latch again becomes transparent. the logic diagram of latch IC 74LS75 is shown below.
Latch plays an important role in microprocessor-based systems. when the microprocessor sends an output, data are available on the data bus for only a few microseconds, therefore, a latch is used to hold data for the peripheral. some of the examples of latch ICs are shown the below-given table.
| IC Number | Description |
|---|---|
| 7475, 7477, 74ls375 | D type bistable latches |
| 74100 | 8 bit bistable latches |
| 74116 | Dual 4 bit latches |
| 74259 | 8 bit addressable latches |
| 74279 | Quad S-R latches |
