Addition and Subtraction in Computer Architecture

Addition and Subtraction in Computer Architecture – As discussed in the earlier section, there are various ways to represent the fixed-point and floating-point numbers. In most computers, negative numbers are represented by the 2’s complement method in fixed-point representation.

For floating point representation, sign magnitude representation is used for the mantissa field. The arithmetic operations related to negative numbers may use complement arithmetic, in which negative numbers are represented by their complements.

Addition and Subtraction with Sign-Magnitude Data

The sign-magnitude representation of data is very common since it is used in daily life for arithmetic calculations. Let us assume there are two signed numbers with magnitudes A and B. When addition and subtraction operations are performed on these two signed numbers, there are eight different conditions as shown in the table below. These conditions depend on the sign of numbers and the operation to be performed.

Operation	Add Magnitude	Subtract Magnitude When A > B	Subtract Magnitude When A < B	Subtract Magnitude When A = B
(+A) + (+B)	+ (A + B)
(+A) + (-B)		+ (A-B)	-(B-A)	+(A-B)
(-A) + (+B)		– (A-B)	+(B-A)	+(A-B)
(-A) + (-B)	– (A + B)
(+A) – (+B)		+ (A-B)	-(B-A)	+(A-B)
(+A) – (-B)	+ (A + B)
(-A) – (+B)	– (A + B)
(-A) – (-B)		-(A-B)	+(B-A)	+(A-B)

Hardware Implementation

For the implementation of addition and subtraction operations, the two numbers should be stored in two registers. Let A and B be two registers that store the magnitudes of numbers. Let A and B be two flip-flops that store the sign bits of the respective numbers. The figure below shows the basic implementation of addition and subtraction.

The result of the operation is stored in register A, and the final output carry in flip-flop E. There are more flip-flop, named AVF, that holds the overflow bit when A and B are added. The above figure shows that the addition of two numbers stored in register A and register B is performed through the parallel adder. The sum output (S) of the adder is then stored in register A.

The complement block provides the complement of the number stored in register B according to the mode control signal. The mode control line is also connected to the input carry of the parallel adder block. The complementer block consists of EX-OR circuits. The working of the EX-OR gate with one input, 0 or 1, is shown in the figure below.

When the control input (M) is low (‘0’), the output of the complementer will be the same as register B, and the input carry for the adder is also zero. Hence, the output of the parallel adder will be A + B +0 (zero). This is stored in register A again. Similarly, when the control input (M) is high (“1”), the 1’s complement of B is applied to the parallel adder, the input carry is ‘1’, hence the output of the parallel adder will be A+B+1 = A-B.

Hardware Algorithm

The above table of (Addition and Subtraction conditions for two signed numbers) shows that for the addition operation, when the signs of register A and register B are the same, add the two magnitudes and attach the sign of A to the result. When the signs of A and B are different, compare the magnitude and find the difference between the two.

The sign bits of register A and register B are stored in the flip-flops A_s and B_s. The two signs A and B are compared by an EX-OR gate. If the output of the gate is 0, the signs are identical; if it is 1, the signs are different. For the addition operation, the magnitudes are added, and the result is stored in the EA register. The EA register is a combination of an E flip-flop and register A. The carry in E after addition constitutes an overflow if it is equal to 1. The value of E is transferred into the overflow flip-flop AVF.

Similarly, for the subtraction operation, when the sign flip-flops, As and Bs are different, add the two magnitudes and attach the sign of A to the result. When the signs of A and B are identical, compare the magnitude and find the difference between the two. Attach the sign of a large number to the result. The magnitudes are subtracted using the 2’s complement method. No overflow can occur if the numbers are subtracted, so AVF is reset to 0.

The flip-flop E can be used to determine the larger magnitude if the subtraction operation is performed. If E=1, the magnitude of A is larger than the magnitude of B. This indicates that the number in register A after subtraction (A ← A-B) is correct. If E=0, the magnitude of A is smaller than the magnitude of B. This indicates that the number in register A after subtraction (A ← A-B) is the complement of the required result (A ← B-A). For this case, it is necessary to take the 2’s complement of the value in register A. This can be done with one micro operation A ← A + a. If the magnitudes of A and B are equal, make the sign of the result positive. It means the result must be +0, not -0.

The algorithm for the subtraction operation is similar to the addition algorithm, except for the sign comparison. The procedure to be followed for identical signs in the addition algorithm is the same as for different signs in the subtraction algorithm, and vice versa. The figure below shows the flowchart for addition and subtraction operations.

Addition and Subtraction with Signed 2’s Complement Data

The signed 2’s complement representation is obtained by taking the 2’s complement of the positive number, including its sign bit. The operation for the signed 2’s complement system does not require a comparison or subtraction; only addition and complementation are required. Therefore, the procedure is very simple and can be given as follows:

Add the two numbers, including sign bits, and discard any carry out of the sign (leftmost) bit position. The following are some examples of signed 2’s complement addition and subtraction.

+9  00001001
+15 00001111
___ ________
+24 00011000
____________

-9  11110111
+15 00001111
___ ________
+6  00000110
____________

+9  00001001
-15 11110001
___ ________
-6  11111010
____________

-9  11110111
-15 11110001
___ ________
-24 11101000
____________

Hardware Implementation

Hardware implementation for addition and subtraction with signed 2’s complement is almost similar to the signed magnitude representation. The basic difference between these two is that the sign bits are not separate from the rest of the register in signed – 2’s complement representation. Nomenclature is changed here to make the difference. Register A is named as AC (accumulator), and register B is named as BR. The left-most bit in AC and BR represents the sign of the numbers. The two sign bits are added or subtracted together with the other bits in a complementer and parallel adder.

There is an overflow flip-flop, which is set to 1 if there is any overflow. An overflow occurs when two -bit numbers are added, and the sum occupies (n+1) bits. The overflow can be detected by EX-ORing the last two carries out of the addition. The output carry is discarded in this case. The following figure shows the hardware implementation for signed 2’s complement addition and subtraction.

Hardware Algorithm

The algorithm for the addition and subtraction of two binary numbers is shown in the figure below. The flow chart shows that the sum is obtained by adding the contents of AC and BR, including their sign bits. The subtraction is performed by adding the 2’s complemented contents of BR to the AC. Taking the 2’s complement of BR has the effect of changing a positive number to negative, and vice versa.

An overflow flip-flop status must be checked during operation because the two numbers added could have the same sign. If there is an overflow, there will be an erroneous result in the AC register.

Addition & Subtraction with Floating Point Data

Arithmetic operations with floating-point data are more complicated than the fixed point data. The hardware required to implement these operations is also complex. Also, their execution takes longer time. Therefore, to perform an operation on the floating-point numbers, the exponents of the two normalized numbers must be made equal. This can be achieved by right shifting the mantissa field of a smaller number by a number of places which is equal to the difference in exponents. This process is named scaling or alignment of numbers.

Hardware Implementation

The difficulty in adding or subtracting two floating-point numbers is that they may have different exponents. Therefore, before the two numbers are added or subtracted, their exponents must be equalized. The hardware implementation is shown in the figure below. This shows that the result of the comparison of the magnitude of two exponents directs the alignment unit to shift the proper mantissa. Both mantissas are then fed to the add/subtract unit for the actual computation. The result is normalized and rounded when needed.

Hardware Algorithm

In general, the addition of two floating-point numbers may result in an unnormalized number. In such a case, the resulting number should be normalized by shifting the resulting mantissa and adjusting the resultant exponent. This is performed in the result normalization round unit, as shown in the figure below. Whenever an exponent is increased or decreased, overflow and underflow should be checked. The size of the resulting mantissa should also be checked. If the resulting mantissa requires more bits than its field, it must be rounded to the appropriate number of bits. The flow chart for the normalization round is shown in the figure below.