CPU Bus Architecture | Computer Architecture

CPU Bus Architecture – The central processing unit (CPU) consists of ALU, register array and control unit. The information is transferred between them. Hence path must be provided for information communication.

The number of wires will be exercised if separate lines are used between different units. A common bus architecture is an efficient way for transferring information between them. A common bus architecture for CPU is shown in below figure.

The CPU bus architecture includes two multiplexers and one decoder. The output of each register is connected to multiplexer to form the two 8-bit buses A and B. The selection lines in cach multiplexer select one register or the input data for the particular bus. Bus A and Bus B form the inputs to the common ALU.

The operation to be performed in the ALU is selected by the selection lines of ALU (OPR). The result of the micro operation performed is available for output data and also goes into the inputs of registers. The register that receives the information from the output bus is selected by the decoder. The decoder activates one of the register at a time. The control unit operates the CPU bus architecture by directing the information flow through registers and the ALU by selecting the various components in the system.