Adder Circuits in Computer Architecture

Adder Circuits in Computer Architecture – The addition operation is one of the major functions of the arithmetic logic unit (ALU). By increasing the speed of addition, the speed of the ALU, and then the speed of the overall machine can be increased. Speed and cost of any system are directly related to the complexity of the system. There are many types of adder circuits, and their complexity varies according to their designs.

Adder Circuits Types

1. Half and Full Adder
2. Ripple Carry Adder (Parallel Adder)
3. Carry Look Ahead Adder
4. Serial Adder
5. BCD Adder

Half and Full Adder

The basic digital arithmetic operation is the addition of two binary digits. A combinational circuit that performs the arithmetic addition of two bits is called a half adder. The combinational circuit that performs the addition of three bits (two significant bits and one previous carry) is called a full adder. The figure below shows the truth tables, Boolean expressions, and block diagrams of half adder and full adder circuits.

X Y	S C
0 0	0 0
0 1	1 0
1 0	1 0
1 1	0 1

X Y Cin	S C
0 0 0	0 0
0 0 1	1 0
0 1 0	1 0
0 1 1	0 1
1 0 0	1 0
1 0 1	0 1
1 1 0	0 1
1 1 1	1 1

Ripple Carry Adder (Parallel Adder)

A full adder can add two bits with carry. By using a parallel adder, two binary numbers of n bits each can be added. Let the binary numbers be A₃A₂A₁A₀ and B₃B₂B₁B₀. So first add A₀ and B₀, then add A₁ and B₁ with the previous carry generated. Similarly, add all other bits as shown in the figure below.

As shown in the above figure, two bits are added in parallel with the carry from the previous adder. The input of the full adder FA0 is given logic ‘0’. The carry out from one full adder is connected to the carry in of the next full adder. Such a carry propagation is called ‘ripple carry,’ and this adder is named as a ripple carry adder or a parallel adder.

Carry Look Ahead Adder

In the parallel binary adder, the carry generated by the i^th adder is fed as carry input to the (i+1)^th adder. In this adder, the final output (C₄S₃S₂S₁S₀) is available only after the carry is propagated through each of the adder i.e., from LSB to MSB adder. This leads to a time delay in the addition process. This is known as carry propagation delay.

One method for reducing the carry propagation delay time is to employ faster gates with reduced delays. Another method, which is widely used, is designed with the principle of look-ahead carry. This method utilizes logic gates to look at the lower-order bits of the augend and addend if a higher-order carry is to be added. It uses two functions: carry generate (G_i) and carry propagate (P_i).

Gi = A_i B_i
and P_i = A_i ⊕ B_i

The output sum and carry of the i^th full adder can be expressed as

Si = A_i ⊕ B_i ⊕ C_{in i}
= P_i ⊕ C_{in i}

and C_{out i + 1} = A_i B_i + B_iC_{in i} + C_{in i}A_i
= A_i B_i + C_{in i} ( A_i ⊕ B_i )
= G_i + C_{in i} P_i

The look-ahead carry generator provides all carry out in only two gate delay times. Now, this look-ahead carry generator can be employed in an adder circuit to make addition faster. A four-bit look-ahead carry adder is shown in the figure below.

Serial Adder

The sum of two n-hit numbers, A and B, can also be generated in a serial fashion. The serial addition method uses only one full adder circuit and a storage device to hold the generated output carry. The pair of bits in A and B (which are stored in the right shift register) is transferred serially, one at a time, through the single full-adder to produce a string of output bits for the sum. The stored output carry from one pair of bits is used as an input carry for the next pair of bits, as shown in the figure below.

The addition of two n-bit numbers starts from the least significant bits and progresses step by step to the most significant bits in different time sequences. Initial by the D flip-flop is cleared.

BCD Adder

Computers that perform arithmetic operations directly in the decimal number represent decimal numbers in binary coded forms (BCD). The BCD adder is a combinational circuit that adds two BCD digits and gives the output in BCD. There are 9 input lines, of which 4 bits are for the first BCD number, 4 bits are for the second BCD number, and one for carry. It has five output line in which 4 lines are for the result in BCD and 1 extra line since the maximum answer in BCD can be 19 (9+9+1=19).

The block diagram for the BCD adder is shown in the figure below. This adder has two 4-bit BCD inputs B₃B₂B₁B₀, A₃A₂A₁A₀, and a carry input C_in. It also has a 4-bit sum output S₃S₂S₁S₀ and a carry output C_out. The sum output is also in BCD form.

A BCD adder circuit must be able to do the following:

1. Add two 4-bit BCD numbers using straight binary addition.
2. If the 4-bit sum is equal or less than 9, the sum is a valid BCD number and no correction is needed.
3. If the 4-bit sum is greater than 9 or if a carry is generated from the sum. The sum is an invalid BCD number. Then, the digit 6 (0110₂) should be added to the sum to produce the valid BCD result.

The above figure shows a BCD adder based on a 4-bit parallel adder. In addition to two 4-bit parallel adders, the adder includes some gates to perform logic correction for intermediate sum digits that are greater than 9 (1001₂). In such cases, 6 (0110₂) is added to the sum to produce the final correct result.