General Register Organization in Computer Architecture

General Register Organization in Computer Architecture – Storing pointers, counters, return addresses, temporary results, and partial products during multiplication operation into the memory is not efficient; such applications are time-consuming because memory access is the most time-consuming operation in a computer.

When a large number of registers are included in the CPU, it is most efficient to connect them through a common bus system. The registers communicate with each other not only for direct data transfers, but also while performing various microoperations. Hence, it is necessary to provide a common unit that can perform all the arithmetic, logic, and shift microoperations in the processor.

A bus organization for seven CPU registers is shown in the figure below. The output of each register is connected to two multiplexers (MUX) to form the two buses A and B. The selection lines in each multiplexer select one register or the input data for the particular bus. The A and B buses form the inputs to a common arithmetic logic unit (ALU). The operation selected in the ALU determines the arithmetic or logic microoperation that is to be performed.

The result of the microoperation is available for output data and also goes into the inputs of all the registers. The register that receives the information from the output bus is selected by a decoder. The decoder activates one of the register load inputs, thus providing a transfer path between the data in the output bus and the inputs of the selected destination register. The control unit that operates the CPU bus system directs the information flow through the registers and ALU by selecting the various components in the system.

SELA (3 bit)

SELB (3 bit)

SELD (3 bit)

OPR (3 bit)

For example, to perform the operation.

R1 ← R2 + R3

The control must provide binary selection variables to the following selector inputs:

1. MUX A selector (SELA): To place the content of R2 into bus A.
2. MUX B selector (SELB): To place the content of R3 into bus B.
3. ALU operation selector (OPR): To provide the arithmetic addition A + B.
4. Decoder destination selector (SELD): To transfer the content of the output bus into R1.

The four control selection variables are generated in the control unit and must be available at the beginning of a clock cycle. The data from the two source registers propagate through the gates in the multiplexers and the ALU, to the output bus, and into the inputs of the destination register, all during the clock cycle interval. Then, when the next clock transition occurs, the binary information from the output bus is transferred into R1. To achieve a fast response time, the ALU is constructed with high-speed circuits. The buses are implemented with multiplexers or three-state gates

Control Word

There are 14 binary selection inputs in the unit, and their combined value specifies a control word. The 14-bit control word is defined in the figure below. It consists of four fields. Three fields contain three bits each, and one field has five bits. The three bits of SELA select a source register for the A input of the ALU. The three bits of SELB select a register for the B input of the ALU. The three bits of SELD select a destination register using the decoder and its seven load outputs. The five bits of OPR select one of the operations in the ALU. The 14-bit control word, when applied to the selection inputs specify a particular microoperation.

The encoding of the register selections is specified in a table below.

Binary Code	SELA	SELB	SELD
000	Input	Input	None
001	R1	R1	R1
010	R2	R2	R2
011	R3	R3	R3
100	R4	R4	R4
101	R5	R5	R5
110	R6	R6	R6
111	R7	R7	R7

The 3-bit binary code listed in the first column of the table specifies the binary code for each of the three fields. The register selected by fields SELA, SELB, and SELD is the one whose decimal number is equivalent to the binary number in the code. When SELA or SELB is 000, the corresponding multiplexer selects the external input data. When SELD=000, no destination register is selected, but the contents of the output bus are available in the external output. The ALU provides arithmetic and logic operations. In addition, the CPU must provide shift operations.

Example of Micro-operations

A control word of 14 bits is needed to specify a microoperation in the CPU. The control word for a given microoperation can be derived from the selection variables. For example, the subtraction microoperation given by the statement.

R1 ← R2 - R3

Here, R2 specifies the A input of the ALU, R3 specifies the B input of the ALU, R1 specifies the destination register, and an ALU operation to subtract A – B. The control word for this microoperation and a few others are listed in the table below.

Micro-operation	SELA	SELB	SELD	OPR	Control word
R1 ← R2 – R3	R2	R3	R1	SUB	010 011 001 00101
R4 ← R4 V R3	R4	R5	R4	OR	100 101 100 01010
R6 ← R6 + 1	R6	—	R6	INCA	110 000 110 00001
R7 ← R1	R1	—	R7	TSFA	001 000 111 00000
Output ← Input	R2	—	None	TSFA	010 000 000 00000
Output ← Input	Input	—	None	TSFA	000 000 000 00000
R4 ← sh1 R4	R4	—	R4	SHLA	100 000 100 11000
R5 ← 0	R5	R5	R5	XOR	101 101 101 01100