Memory Reference Instructions in Computer Architecture

Memory reference instructions in computer architecture – The microoperations needed for the execution of each instruction, it is necessary that the function that they are intended to perform be defined precisely. Some instructions have an ambiguous description.

This is because the explanation of an instruction in words is usually lengthy, and not enough space is available in the table for such a lengthy explanation. We will now see that the function of the memory reference instructions can be defined precisely by means of register transfer notation.

	Symbol	Operation decoder	Symbolic description
1.	AND	D0	AC ← AC ^ M [AR]
2.	ADD	D1	AC ← AC + M [AR], E ← Cout
3.	LDA	D2	AC ← M[AR]
4.	STA	D3	M[AR] ← AC
5.	BUN	D4	PC ← AR
6.	BSA	D5	M[AR] ← PC, PC ← AR + 1
7.	LSA	D6	If M[AR] + 1 = 0 then PC ← PC + 1

The decoded D: for i = 0,1,2,3,4,5 and 6 from the operation decoder that belongs to each instruction is included in the table. The effective address of the instruction is in the address register AR and was placed there during timing signal T2 when I=0, or during timing signal T3 when I = 1. The execution of the memory-reference instructions starts with the timing signal T4.

The symbolic description of each instruction is specified in the table in terms of register transfer notation. The actual execution of the instruction in the bus system will require a sequence of microoperations. This is because data stored in memory cannot be processed directly. The data must be read from memory to a register where it can be operated on with logic circuits. We now explain the operationof each instruction and list the control functions and microoperations needed for their execution.

AND to AC: This is an instruction that performs the AND logic operation on pairs of bits in AC and the memory word specified by the effective address. The result of the operation is transferred to the AC. The microoperations that execute this instruction are:

D0T4 : DR ← M[AR]
D0T5 : AC ← AC^DR, SC ← 0

ADD to AC: This instruction adds the content of the memory word specified by the effective address to the value of AC. The sum is transferred into AC, and the output carry Cout is transferred to the E (extended accumulator) flip-flop. The microoperations needed to execute this instruction are

D1T4 : DR ← M[AR]
D1T5 : AC ← AC + DR, E ← Cout, SC ← 0

LDA: Load to AC: This instruction transfers the memory word specified by the effective address to AC. The microoperations that execute this instruction are:

D2T4 : DR ← M[AR]
D2T5 : AC ← DR, SC ← 0

STA: Store AC: This instruction stores the content of AC into the memory word specified by the effective address.

D3T4 : M[AR] ← AC, SC ← 0

BUN: Branch Unconditionally: This instruction transfers the program to the instruction specified by the effective address. The BUN instruction allows the programmer to specify an instruction out of sequence, and the program branches (or jumps) unconditionally.

D4T4 : PC ← AR, SC ← 0

BSA: Branch and Save Return Address: This instruction is useful for branching to a portion of the program called a subroutine or procedure. When executed, the BSA instruction stores the address of the next instruction in sequence (which is available in PC) into a memory location specified by the effective address.

M[AR] ← PC, PC ← AR + 1
M[135] ← 21, PC ← 135 + 1 = 136

It is not possible to perform the operation of the BSA instruction in one clock cycle when we use the bus system of the basic computer. To use the memory and the bus properly, the BSA instruction must be executed with a sequence of two microoperations:

D5T4 : M[AR] ← PC, AR ← AR + 1
D5T5 : PC ← AR, SC ← 0

ISZ: Increment and Skip if Zero: These instruction increments the word specified by the effective address, and if the incremented value is equal to 0, PC is incremented by 1. Since it is not possible to increment a word inside the memory, it is necessary to read the word into DR, increment DR, and store the word back into memory.

D6T4 : DR ← M[AR]
D6T5 : DR ← DR + 1
D6T4 : M[AR] ← DR If (DR=0) then (PC ← PC+1), SC ← 0

Below given flowchart showing all micro-operations for the execution of the seven memory-reference instructions is shown in below figure. The control functions are indicated on top of each box.

The micro-operations that are performed during time T₄, T₅, or T₆ depend on the operation code value. This is indicated in the flowchart by six different paths, one of which the control takes after the instruction is decoded. The sequence counter SC is cleared to 0 with the last timing signal in each case. This causes a transfer of control to timing signal T₀ to start the next instruction cycle.