Input Output Processor in a Computer Architecture

Input Output Processor in a Computer Architecture – An input output processor can be defined as a processor with direct memory access (DMA) capability that communicates with I/O devices. An I/O processor is also called an I/O controller, channel controller, or peripheral processing units (PPUs). An I/O processor usually incorporates several DMA controllers within its circuitry. The I/O processor takes care of input and output tasks, relieving the CPU from the data management involved in I/O data transfer.

The basic working of an I/O processor is similar to the CPU except that it is designed to handle only I/O processing. The CPU does not have any direct connection with I/O devices if an I/O processor is present in the system. The CPU instructs the I/O processor to perform the desired operation with I/O devices. If the CPU wants to read data from an input device or initiate a block transfer between memory and I/O devices, the CPU instructs the I/O processor to perform the operation.

The I/O processor coordinates the actual data transfer. The only exception is that the CPU coordinates the transfer of data between itself and the I/O processor.

The I/O processor is similar to a DMA controller, with the difference that the DMA controller is initialised and set up entirely by the CPU, but the I/O processor has its own instructions. It can fetch and execute its own instructions. In addition, the I/O processor can perform other processing tasks, such as arithmetic, logic, branching, and code translation. 

I/O processor is primarily a communication processor designed to link I/O devices to the computer system. The I/O processor has an instruction set with limited capabilities. In this configuration, a computer system can be divided into a memory unit, a CPU, and one or more I/O processors. This is shown image below. Similar to the DMA controller, the I/O processor is situated between the I/O devices and the rest of the system. Unlike the DMA controller, however, the I/O processor connects to more than one I/O device. 

The I/O devices are connected together on an I/O bus, as opposed to the regular system bus. Thus, one I/O processor can coordinate transfers from several different I/O devices.

There are various I/O devices connected to the I/O processor. The data format of these I/O devices may differ from the data format of the CPU and memory. Therefore, compatibility of data format during the data transfer between the I/O device and CPU or memory is also taken care of by the I/O processor. For example, if an input device provides the data of 2 byte word and the CPU except 4 byte words. Then the I/O processor takes two words from the input device and packs them into four bytes before transferring them to the CPU. Data is collected in the I/O processor at the device rate and bit capacity while the CPU is executing its own program. After the input data is assembled into a memory word, they are transferred into memory. In the same manner, an output word transferred from memory to the I/O processor is directed from the I/O processor to the output device at the device rate and bit capacity.

I/O Processor Commands

When the CPU deals with the DMA, the initialisation process must be completed by writing the values into the DMA controller registers. Unlike this, the CPU issues a series of I/O instructions to the I/O processor. These instructions are often called commands to distinguish them from CPU instructions. However, an instruction and a command have similar functions. These commands are stored in memory, and the CPU only instructs the I/O processor where to find the commands in memory at the time of execution. In general, commands may fall into three categories: 

1. Block transfer command 
2. Arithmetic, logic, and branch command 
3. Control commands 

Block Transfer Command: As the name suggests, these commands move blocks of data. These commands are just like the DMA transfer with the necessary parameters. These commands can be used to swap pages in and out of physical memory, and to load programs from disk to memory. 

Arithmetic, Logic, and Branch Command: These commands are basically used to manipulate data so that it can be used by the CPU. The branch commands can be used to jump from one location to another within the command program. It is similar to the branch instruction in CPU programs. Consider an example of a CPU that has a data bus of 16-bits.

If the system is connected with an input device with an 8-bit input port, one general method to read the data from the input device is that the CPU reads two separate data and concatenates them into a single 16-bit word. This is a time-consuming process for the CPU, so it can instruct the I/O processor to operate for reading two 8-bit data and then concatenate them into a single 16-bit word through arithmetic and logic commands.

Control commands: These are usually hardware-dependent and critical to the proper functioning of the computer system. These commands can control the physical behaviour of the I/O devices connected. For example, a control command can instruct the pointer to print a page or rewind the tape on a tape drive.

I/O Processor Functioning

DMA controller and the I/O processor are both designed for I/O communications. But their basic functioning is different. The I/O processor can perform several I/O transfers parallely whereas the DMA controller sequentially performs those transfers.

For example, if three I/O devices want to communicate with the CPU. A system with a DMA controller but no I/O processor would first perform the I/O transfer with the first I/O device by following the initialization operation. Once the first I/O transfer is completed, the initialisation process for the second I/O transfer will be done similarly, third I/O transfer will be completed.

In contrast to DMA functioning, the CPU in a system with an I/O processor would write the commands needed to perform all three I/O transfers into a contiguous block of memory and pass a pointer to this block to the I/O processor. This reduces the overhead associated with setting up the transfers.

While the I/O processor is performing its I/O transfers, the CPU can continue to perform other operations. Once the I/O processor completes I/O transfers, it must be capable of informing the CPU through an interrupt. This interrupt would cause the CPU to read the data either directly from the I/O processor or from a predetermined memory location in which the I/O processor stored the data.

The polling method can also be used to inform the CPU about the completion of an I/O transfer. The I/O processor could set a value in a memory location signifying that its data is ready. The CPU checks the memory location in a predefined time interval and if found set, then reads the data from the I/O processor directly or from a predetermined memory location.

CPU-IOP Communication

For CPU and I/O processor communication, the memory unit acts as the message center. In memory, the CPU and I/O processor can write information for others to read. A simplified example of CPU-I/O processor communication is shown in the image below. However, many operating details are not included in this example for simplicity.

The sequence of operations may be carried out in a CPU-IOP communication as follows: 

1. The CPU executes an instruction to test the IOP path. 
2. In response to this check, the I/O processor stores the status word in memory. The status of I/O devices and the I/O processor is indicated by the corresponding bits of the status word. 
3. Now the CPU checks the status word from memory, which is stored by the I/O processor. If it found I/O processor status ready, it sends the instruction to start the I/O transfer.
4. When the I/O processor receives the start I/O transfer command, along with the address of the I/O service routine. It executes the I/O program. The I/O processor refers to стогу for I/O transfer using the DMA mode of transfer. 
5. The CPU continues with another program while the I/O processor is busy with the I/O program.
6. At the end of the I/O transfer, the I/O processor interrupts the CPU. 
7. After interrupting, the CPU requests the CPU for status word.
8. Now the I/O processor writes the status word in a predefined memory location. The status bits of the status word indicate whether the I/O transfer was completed or same errors occurred during transfer. 
9. CPU reads the status word and checks whether the I/O transfer is completed without errors or not 

As above, the I/O processor and the CPU are competing for the use of memory, so the number of devices that can be in operation is limited by the access time of the memory.