Instruction Pipeline in Computer Architecture

YASH PAL,

Instruction Pipeline in Computer Architecture – The pipeline processing can occur not only in the data stream but in the instruction stream as well. In conventional computers based on the Von Neumann architecture, instruction execution involves several steps.

These steps include fetching and decoding the instruction, calculating the effective address, fetching the operands, executing the instruction, and finally storing the result at the desired memory location. These operations were performed in the prespecified sequence and make the system slower.

Instruction Pipeline

An instruction pipeline increases the performance of a processor by overlapping the processing of several different sub-operations. Often, this is done by dividing the instruction execution process into several segments. There are certain difficulties that are faced in obtaining the maximum rate.

Different segments take different times to complete the sub-operation. Some segments may be skipped for certain sub-operations. The design of an instruction pipeline will be efficient if the instruction cycle is divided into segments of equal duration.

Phases of Instruction Execution

In the simplest way, there are only two phases to process any instruction: (i) instruction fetch and (ii) execution. But computers with complex instructions require more phases in addition to the instruction fetch and execution. In most of the cases, the computer needs to process each instruction with the following phases

  1. Instruction Fetch (IF): The processor fetches or retrieves the instruction code from cache or main memory.
  2. Instruction Decoding (ID): This phase includes the decoding of instructions. Effective address of the operands is also calculated if required, in this phase.
  3. Operand Fetch (OF): Retrieval of any required operands from memory is done in this phase.
  4. Execution (EX): In this phase, execution of the fetched instruction takes place.
  5. Store Result (ST): This phase stores the result in the proper place.

An instruction pipeline overlaps processes of various phases for different instructions to reduce the total processing time.

Consider an example of five instructions program. It is assumed that the processor has separate instruction and data memories. During the first clock pulse, instruction i1 is fetched from memory. Within the second cycle, instruction i1 is decoded, and instruction i2 is fetched from memory. This process continues until all the instructions are executed. This is shown in the table below.

Instru
ction		CLOCK
PULSE
1st		CLOCK
PULSE
2nd		CLOCK
PULSE
3rd		CLOCK
PULSE
4th		CLOCK
PULSE
5th		CLOCK
PULSE
6th		CLOCK
PULSE
7th		CLOCK
PULSE
8th		CLOCK
PULSE
9th
i1IFIDOFEXST
i2–IFIDOFEXST
i3––IFIDOFEXST
i4–––IFIDOFEXST
i5––––IFIDOFEXST
Execution of the Instruction pipeline

Related Questions and Answers

Define instruction pipeline.

An instruction pipeline is a pipeline structure that operates on a stream of instructions by overlapping the fetch, decode, and execute phases of the instruction cycle.

Write the five most common phases of instruction execution.

In most of the cases, the computer needs to process each instruction with the following phases.
(i) Instruction fetch
(ii) Instruction Decoding
(iii) Operand fetch
(iv) Execution
(v) Store result

What are the limitations of the instruction pipeline?

These three major limitations of the instruction pipeline
(i) Resource conflict
(ii) Data Dependency
(iii) Branch Difficulties

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