Data Representation in Computer Architecture

Data Representation in Computer Architecture – Modern computers are digital systems. They accept electrical signals as a discrete value rather than as analog quantities. A digital system’s signaling convention determines the interpretation of analog signals into digital signals.

The most common signalling convention determines the interpretation of analog signals into digital signals. The most common signaling convention is shown in the figure below. Lower voltages, between 0V and V_OL, are named as logic ‘0’ and higher voltages, between V_IH and V_cc, are named as logic ‘1’. So in digital systems, there are two signals: Logic ‘0’ and logic ‘1’. The region between V_IL and V_IH is known as the forbidden region because it is not possible to predict the signal in this region, whether it is logic ‘0’ or logic ‘1’.

The digital system that maps each electrical signal into two signals is known as the binary system. The information carried by each signal is called a bit (short form of binary digit). Systems with more values per signal are possible, but the complexity of designing the circuit will increase to interpret and reproduce these signals. For this reason, almost all the digital systems are binary.

The arithmetic and logic unit (ALU) performs the operations on the information that is stored in binary format. The binary information or data may be represented as fixed-point or floating-point data. The arithmetic instruction specifies the operation to be performed on the data. There are four basic arithmetic operations: addition, subtraction, multiplication, and division. From these four operations, other arithmetic operations can be formulated.

Data Representation

The arithmetic operations are performed by the arithmetic processor, which is a part of the processor unit. The data is stored in the processor registers. The data type is specified in the definition of the instruction. The data may be in fixed-point or floating-point form. Fixed-point numbers may be integers or fractions. Integer numbers can further be classified as positive and negative numbers. Floating point numbers are expressed in basic format, which is a number multiplied by a constant raised to the same integer power (exponent). The data representation is shown in the figure below.

Fixed Point Data Representation

In fixed-point data representation, all numbers are represented as a fraction or an integer. Fixed-point data does not contain any information regarding the position of the point (binary or decimal). Fixed-point data may further be classified into two categories:

Integer
Fraction

If the point is at the extreme right of the data, the number is said as integer. The example of an integer number is 108 or 108.0; Whereas, if the point is at the extreme left, the number is known as a fraction like 0.108. Any fixed point number does not have an integer as well as fraction part in itself. In many applications, computer uses fractions. The digital system has to take care of fractions in applications.

Any fixed point number can be positive or negative. In the decimal number system, a sign of ‘+’ for positive and ‘-‘ for negative is placed before the number. But in computers, such notations are not applicable. One of the ways to represent a positive number is that a 0 (zero) is placed before the binary number. There are two ways to represent a negative number:

Sign-Magnitude Representation
2’s Complement Representation.

Sign-Magnitude Representation

In this representation, the leftmost bit of the binary number indicates the sign of the number. This bit is known as the sign bit. For a positive number, this bit is considered as 0, and for a negative number, it is 1. The remaining bits of the number represent the absolute value (or magnitude) of the number. An N-bit sign-magnitude number can represent quantities from-(2^N-1-1) to +(2^N-1-1).

The sign-magnitude representation has the advantage that taking the negative of a number is very easy-just invert the sign bit. The sign of the number can be determined by simply examining the sign bit of the number. This representation makes multiplication and division operations easier, but addition and subtraction operations harder.

Note: There are two representations for the number 0 in sign-magnitude representation: +0 and-0. +0 has a value 0 in the magnitude field and a positive sign bit 0 in the sign field. Whereas -0 has a value 0 in the magnitude field and a negative sign bit 1 in the sign field.

2’s Complement Representation

2’s complement of any number can be obtained by inverting each bit of the unsigned representation of the number and adding 1 to the result. Any overflow must be discarded that does not fit in the width of representation.

The 2’s complement of a binary number is equal to the 1’s complement of the number plus one.

2’s compliment = 1’s compliment +1

2’s complement representation has a number of useful properties, like negating a number gives the original number. Therefore, no special hardware is required. 2’s complement representation has only one representation for zero. This reduces the hardware requirement to detect the sign of zero.

An n-bit 2’s complement number can represent values from (2^N-1) to + (2^N-1-1). This asymmetry occurs because there is only one representation for zero.

Note: Adding the representation of positive and negative 2’s complement of the same number gives the result as 0.

Example 1: What are the binary and hexadecimal representations of the decimal number 35?

Solution: To convert a decimal number to binary, express the number as a sum of values that are powers of two:
35=32+2+1
=1 x 2⁵ + 0 × 2⁴ + 0 × 2³ + 0 × 2² + 1 × 2¹ + 1 × 2⁰.

Therefore, the binary representation of 35 is 0b 100011.

To convert a binary number into a hexadecimal number, make a group of 4 bits from right most side. Therefore, the hexadecimal representation of 35 (0b 0010 0011) is 0h23.

Example 2: Convert the following decimal numbers to 8-bit sign-magnitude representation:

Solution: In sign-magnitude representation, positive numbers are represented by 0 in the sign field and magnitude in the magnitude field. However, negative numbers are represented by 1 at the sign field and magnitude in the magnitude field. Therefore, as calculated in the above first example

+35 (0 010 0011)₂
and -35 (1 010 0011)₂

Example 3: What is the 8-bit 2’s complement representation of -35, and what is the unsigned result of adding the number +35 and-35?

Solution: The 8-bit representation of +35 is 0b 00100011. The 2’s complement of +35 (-35) will be 0b 11011101. Addition of two numbers.

+35 + (-35) =    00100011
               + 11011101 
              ____________
              (1)00000000

Discard the carry and get the result 0.

Floating Point Representation

The floating point representation of a number is used when a number contains an integer as well as a fractional part. It means the floating-point representation of a number has two parts. The first part is a signed, fixed-point number. This is known as the mantissa. The second part gives the position of the decimal or binary point. This is known as an exponent. The example of floating point number, 1234.567, can be represented in terms of mantissa and exponent as follows:

Mantissa    Exponent
+0.1234567  +04

Here, it is important to note that the mantissa part may be a fraction or an integer. In the above example, the exponent part indicates that the actual position of the decimal point is four positions to the right of the indicated decimal point in the fraction. This representation is equivalent to the scientific notation +0.1234567×10⁺⁴. This floating point representation is specified in IEEE Standard 754. Floating point representation of a number is indicated as follows

Floating Point Number = m x r^e

Where m is the mantissa, e is the exponent, and r is the radix value. The values of m and e are represented in the register, including the sign. The radix r and radix point position of the mantissa are always assumed.

The IEEE754 standard representation allows a wide range of values to be represented in a relatively small number of bits. In this standard, the default way of rounding is round-to-nearest. The values are rounded to the closest representable number.

The IEEE754 standard specifies a number of bit widths for floating point numbers. There are two most common formats to represent floating point numbers in the IEEE754 standard.

Single precision
Double precision

The single precision format is 32-bit long and contains 1 sign bit, 8 bits of exponent, and 23 bits of fraction. The sign bit contains the sign of the fraction field. Whereas the double precision format has 1 sign bit, 11 bits of exponent, and 52 bits of fraction. The IEEE754 floating point formats are shown in the figure below.

Note: A floating-point number is said to be normalized if the most significant digit of the mantissa is non-zero.

Example 4: How would the following decimal numbers be rounded to three significant digits, using the round to nearest mode?

1.35678
38.79
10.55
6,373

Solution: According to the round-to-nearest mode, look at the lower side if the fourth-most-significant digit is less than 5 and look at the upper side if the fourth-most-significant digit is more than 5. If the fourth most significant digit is 5, then round up the number to make the result even. Therefore

Round up of 1.35678 is 1.36
Round up of 38.79 is 38.8
Round up of 10.55 is 10.6
Round up of 6.373 is 6.37

Example 5: Represent the binary number (+1100.11)₂ with an 8-bit fraction and 6-bit exponent.

Solution: The floating point representation for a binary number is similar to a decimal number, with the difference that the radix is 2 in a binary number instead of 10. Therefore representation is as follows:

Fraction   Exponent
00110011   000101

The fraction part has a 0 in the left-most position to indicate a positive number. The binary point of the fraction follows the sign bit, but it is not shown in the fraction bits. The exponent has the equivalent binary number +5. The floating-point number is equivalent to

m x 2^e = +(0.0110011)₂ x 2⁺⁵