Data Transfer in Computer Architecture

Data Transfer in Computer Architecture – The main issue of data transfer over the bus is the timing issue. The timing for all registers in the basic computer is controlled by a master clock generator.

The clock pulses are applied to all registers in the system. However, the clock pulses do not make any change in the stored information in the registers unless the register is enabled by a control signal.

The data transfer between the bus and registers can be categorized as follows:

1. Synchronous data transfer
2. Asynchronous data transfer

Synchronous Data Transfer

In a synchronous transfer, the data is transferred during a clock cycle which is recognized by both source and destination. The bus interface units are synchronized. If the two units share the same clock, they can be said to be synchronized. The data transfer between the processor’s internal registers is always synchronized because the processor uses a common clock for all its internal registers.

The synchronization can even be achieved by separate clocks with two conditions. First, is that the clock frequency should be approximately the same, and second, is that the synchronization signals must be transmitted at a regular interval between two communicating registers. This signal ensures the synchronization between two registers.

Asynchronous Data Transfer

Asynchronous transfer of data eliminates the requirement of a common clock and replaces it with timing control signals. These signals are generated by the communicating units, which are self-timed and operate with different data transfer rates.

There are two ways of asynchronous transfers:

1. One way control in which one of the two communicating devices initiates all the timing signals
2. Two-way control in which both the communicating devices generate the timing signals. Such timing signals are named the handshaking process.

The advantage of asynchronous transfer is that it provides a high degree of flexibility and can be used with a wide range of devices. The major limitation of such a system is the requirement for more control lines and a complex logic circuit.

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