Priority Interrupt in Computer Architecture

Priority Interrupt in Computer Architecture – The concept of an interrupt is used to handle a variety of problems that arise out of the normal program sequence. Interrupt refers to the transfer of program control from the currently running program to another service program as a result of an externally or internally generated request.

Whenever an interrupt request from any I/O device is accepted by the CPU, it first stores the returning address from the program counter (PC) into a memory stack, and then the program control is transferred to the service routine of that I/O device.

After a program has been interrupted and the service routine been executed, the CPU must return to exactly the same state that it was when the interrupt occurred. The state of the CPU is determined by the contents of the program counter, processor registers, and status bits (Program Status Word). All these contents must be the same before and after the interrupt occurred.

In general, there are various I/O devices attached to the computer, and each device is able to generate an interrupt request to the CPU of that computer. Whenever an interrupt request is originated by an I/O device, the CPU responds to it and provides a service. There is also the possibility that several I/O devices generate the interrupt requests simultaneously. In such a case, the system must also decide which device to service first.

Priority Interrupt

A priority interrupt is a system that establishes a priority over the various I/O devices to determine which I/O device is to be responded to first for simultaneous interrupt requests.

If the CPU is responding to one interrupt service routine and there is another interrupt request, then it is the responsibility of the priority interrupt system to decide whether respond to the new interrupt request or not. In general, slower devices like a keyboard are given lower priority than the higher speed devices. When two I/O devices interrupt the CPU simultaneously, the CPU services the device with higher priority first.

Priority Establishment

As there are various types of I/O devices connected to the CPU, the programs that handle a particular I/O device are also different. There can be more than one interrupt at the same time. To handle such simultaneous requests, some priority mechanism must be used so that the interrupt with the highest priority is attended to first, and likewise others. Priority of simultaneous interrupts can be established by software or hardware methods. Polling method is an example of a software method, whereas the Daisy chaining method is an example of a hardware method of priority establishment.

Service Priority Establishment Methods

Polling (Software) Method

This method is used to find the highest-priority interrupt source by means of software. In this method, there is one common branch address for all interrupts. The program that take care of interrupts begins at the branch address and polls interrupt sources (or I/O devices) in sequence. Their order of testing determines the priority of each I/O device. The I/O device with the highest priority is tested first. If it is generating an interrupt, the program control is transferred to the corresponding service routine; otherwise next lower priority I/O device is tested.

The limitation of this method is that if there are many interrupts, the time required to poll them can exceed the time available to service the I/O device. In such situations, a hardware priority interrupt can be used to speed up the operation.

Hardware Method

A hardware method for priority establishment is used to overcome the limitation of the software method. The hardware method accepts interrupt requests from different I/O devices. Then it determines which of the interrupt request has highest priority and issues an interrupt request to the computer. To make the operation fast, each I/O device has its own interrupt vector to access its own service routine directly. In this method, all decisions are taken on the basis of the hardware priority interrupt unit. The hardware priority function can be established by two types of connections of interrupt lines:

1. Serial Connection 
2. Parallel Connection 

Serial Connection (Daisy-Chaining Priority) Method

This method of establishing priority consists of serially connected I/O devices that request an interrupt. This method may be considered as the hardware implementation of the software (polling) method. The I/O device with the highest priority is placed in the first position, followed by lower-priority devices up to the I/O device with the lowest priority, which is placed last in the chain. The connection of various devices in this method is shown in the figure below. This serial connection of priority establishment is also known as the Daisy-chaining method.

As shown in the figure above, the interrupt request line is common for all I/O devices. If any I/O device generates an interrupt signal, it places logic ‘0’ on the interrupt request. The interrupt request line behaves as a NOR gate, and if any device places logic ‘0’ on this, it transfers a request to the CPU. In response of interrupt request INTR the processor generates an interrupt acknowledgment (INTA). This is connected with the priority input (PI) of the I/O device, which is having highest priority.

If first device does not have any pending interrupts, it transfers the logic to the next lower priority device. If the first device has a pending interrupt, it blocks the acknowledgment signal from the next device by placing a logic ‘0’ in the PO output. It then proceeds to insert its own interrupt vector address (VAD) into the internal data bus for the CPU to use during the interrupt cycle. A device with logic ‘0’ in its priority input (PI) generates a logic ‘0’ in its priority output (PO).

This informs the next device that the acknowledgment signal has been blocked. An I/O device that is requesting an interrupt and has a logic ‘1’ in its priority input (PI) will intercept the acknowledge signal by placing a logic ‘0’ in its PO output. Thus, the device with PI = 1 and PO=0 is the one with the highest priority that is requesting an interrupt, and this device places its vector address (VAD) into the internal data bus.

Parallel Connection

The parallel connection method is based on a register, named the interrupt register. The bits of the interrupt register are set or reset separately by interrupt signals from each I/O device.

Priority is established according to the position of bits in the interrupt register. The parallel connection method also uses another register, known as the mask register. It can control the status of each interrupt request. It can be programmed to disable lower-priority interrupts while a higher-priority device is being serviced. A function that permits the higher priority I/O devices to interrupt the lower priority I/O devices while it is being serviced can also be provided by the mask register.

Hardware Implementation

As discussed earlier, the hardware priority function can be established by two methods :

1. Serial Connection Method and 
2. Parallel Connection Method

Serial Connection Implementation

The serial connection is also known as the daisy-chaining method. The figure below shows the internal logic that must be included within each device when connected in the daisy-chaining scheme.

The above figure shows that the ‘S’ input of the S-R flip-flop is connected with the I/O device. When the I/O device sends an interrupt request to the S-R flip-flop, its output Q gets set. This output is connected to the CPU interrupt request through an open-collector inverter. If the priority input (PI) is set and an interrupt request is generated by an I/O device, the enable signal would get active, and the vector address is transferred. However, if PI=0, both priority out (PO) and enable line to vector address (VAD) are reset.

The device is active when PI=1 and Q=1. This condition places a 0 in PO and enables the vector address for the data bus. Here, it is assumed that each device has its own distinct vector address. If PI=1 and Q=0, then PO=1 and the vector address is disabled. This condition passes the acknowledge signal to the next device through PO.

Parallel Connection Implementation

As discussed, the parallel connection for priority establishment is performed with the use of two registers: the interrupt register and the mask register. The figure below shows the priority logic for a system that has four I/O devices. It consists of a 4-bit interrupt register and a 4-bit mask register. Each bit of the interrupt register is set or reset by the individual I/O devices.

The above figure contains a priority encoder. It is a circuit that implements the priority function. The logic of this circuit is that it provides the output according to the higher-priority interrupt request, if there is more than one interrupt request. The table below shows the truth table of four input priority encoder. 

Input I₀ has the highest priority, so regardless of the values of other inputs. When I₀ = 1, the output generates an output xy = 0. If input I₁ = 1 is provided, I₀ = 0, the output xy = 01, regardless of the values of the other two lower-priority inputs. The output of the priority encoder is used in the vector address. 

Input I0	Input I1	Input I2	Input I3	Output x	Output y	Interrupt Status (IST)	Boolean Function
1	X	X	X	0	0	1
0	1	X	X	0	1	1	x = I’0 I’1
0	0	1	X	1	0	1	x = I’0 I’1 + I’0 I’2
0	0	0	1	1	1	1	(IST) = I0 + I1 + I2 + I3
0	0	0	0	X	X	0