Bus and Memory Transfer in Computer Architecture

Bus and Memory Transfer – A typical digital system has so many registers, and their data paths must be provided to transfer information from one register to another. If we use separate wires for each data path, then system complexity increases. Therefore, to reduce the complexity, an efficient method is adopted for the transfer of information in a multiple register configuration called a common bus system.

Data Transfer using Bus

A bus structure is more efficient for transferring information between registers in a multi-register configuration system. A bus consists of a set of common lines, one for each bit of a register, through which binary information is transferred at a time. Control signals determine which register is selected by the bus during a particular register transfer.

The following block diagram shows a bus system for four registers. It is constructed with the help of four 4×1 multiplexers, each having four data inputs (0 through 3) and two selection inputs (S1 and S2).

We have used labels to make it more convenient for you to understand the input-output configuration of a Bus system for four registers. For instance, output 1 of register A is connected to input 0 of MUX1. The two selection lines, S₁ and S_0, are connected to the selection inputs of all four multiplexers. The selection lines choose the four bits of one register and transfer them into the four-line common bus.

When both of the select lines are at low logic, i.e., S₁S₀ = 00, the 0 data inputs of all four multiplexers are selected and applied to the outputs that form the bus. This, in turn, causes the bus lines to receive the content of registers A since the outputs of these registers are connected to the 0 data inputs of the multiplexers.

Similarly, when S₁S₀ = 01, register B is selected, and the bus lines will receive the content provided by register B. The following function table shows the register that is selected by the bus for each of the four possible binary values of the Selection lines.

S1	S0	Register Selected
0	0	A
0	1	B
1	0	C
1	1	D

A bus system can also be constructed using three-state gates instead of multiplexers. The three-state gates can be considered as a digital circuit that has three gates, two of which are signals equivalent to logic 1 and 0, as in a conventional gate. However, the third gate exhibits a high-impedance state.

The most commonly used three-state gates in the case of the bus system are buffer gates. The graphical symbol of a three-state buffer gate can be represented as:

Control Input	Normal Input	Output
0	0	High Impedance
0	1	High Impedance
1	0	0
1	1	1

The above symbol shows there are two input signals

1. Normal input
2. Control input

The control input signal makes it distinguishable from the normal buffer. When the control signal (active high) goes high, the buffer enables and behaves like any conventional buffer. Whereas when the control signal goes low, the buffer goes to a high state and behaves as if there is no electrical connection between the input and output of the buffer. This is a special feature that is not available in conventional buffers. Because of this feature, a large number of tri-state buffer outputs can be connected with wires to form a common bus line without endangering loading effects.

The diagram below demonstrates the construction of a bus system with three-state buffers.

• The outputs generated by the four buffers are connected to form a single bus line.
• Only one buffer can be in the active state at a given point in time.
• The control inputs to the buffers determine which of the four normal inputs will communicate with the bus line.
• A 2 x 4 decoder ensures that no more than one control input is active at any given point in time.

Note: A bus system will multiplex k registers of n-bits each produce an n-line common bus. For such a bus system, n number of multiplexers with k: 1 size are required.

Memory Transfer

Most of the standard notations used for specifying operations on memory transfer are stated below.

• The transfer of information from a memory unit to the user end is called a Read operation.
• The transfer of new information to be stored in the memory is called a Write operation.
• A memory word is designed by the letter M.
• We must specify the address of the memory word while writing the memory transfer operations.
• The address register is designed by AR, and the data register by DR.
• Thus, a read operation can be stated as:

Read: DR <- M [AR]

In the above expression, Read is the control input. A memory word is symbolized by the letter M. This causes a transfer-out operation from memory word M selected by the address in the AR int data register DR. Below figure shows the basic read operation.

And the corresponding write operation can be stated as:

Write: M [AR] <- R1

The write statement causes a transfer of information from register R1 into the memory word (M) selected by the address register (AR).

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