Input-Output And Interrupt in Computer Architecture

Input-Output and Interrupt in Computer Architecture – A computer can serve no useful purpose unless it communicates with the external environment. Instructions and data stored in memory must come from some input device. Let’s discuss how the interruption of input and output instructions is handled in a computer.

Computational results must be transmitted to the user through some output device. Commercial computers include many types of input and output devices. To demonstrate the most basic requirements for input and output communication, we will use as an illustration a terminal unit with a keyboard and printer.

Input-Output Configuration

The terminal sends and receives serial information. Each quantity of information has eight bits of an alphanumeric code. The serial information from the keyboard is shifted into the input register INPR. The serial information for the printer is stored in the output register OUTR. These two registers communicate with a communication interface serially and with the AC in parallel. The transmitter interface receives serial information from the keyboard and transmits it to INPR. The receiver interface receives information from OUTR and sends it to the printer serially.

The input register INPR consists of eight bits and holds alphanumeric input information. The 1-bit input flag FGI is a control flip-flop. The flag bit is set to 1 when new information is available in the input device and is cleared to 0 when the information is accepted by the computer. The flag is needed to synchronize the timing rate difference between the input device and the computer. The process of information transfer is as follows.

Initially, the input flag FGI is cleared to 0. When a key is struck in the keyboard, an 8-bit alphanumeric code is shifted into INPR, and the input flag FGI is set to 1. As long as the flag is set, the information in INPR cannot be changed by striking another key. The computer checks the flag bit; if it is 1, then information from INPR is transferred in parallel into AC, and FGI is cleared to 0. Once the flag is cleared, new information can be shifted into INPR by striking another key.

The output register OUTR works similarly, but the direction of information flow is reversed. Initially, the output flag FGO is set to 1. The computer checks the flag bit; if it is 1, the information from AC is transferred in parallel to OUTR, and FGO is cleared to 0. The output device accepts the coded information, prints the corresponding character, and when the operation is completed, it sets FGO to 1. The computer does not load a new character into OUTR when FGO is 0 because this condition indicates that the output device is in the process of printing the character.

Here is the final flowchart of the instruction cycle, which includes the interrupt cycle for the basic computer.

Here we have control functions and micro-operations for a basic computer that are commonly used during input/output configuration.

Fetch R'T0: AR ← PC
      R'T1: IR ← M[AR], PC ← PC + 1

Decode R'T2: D0,...,D7 ← Decode IR(12-14)
             AR ← IR (0-11), I ← IR(15)

Indirect D'7IT3: AR ← M[AR]

Interrupt:
    T'0T'1T'2(IEN)(FGI+FGO): R ← 1
                        RT0: AR ← 0, TR ← PC
                        RT1: M[AR] ← TR, PC ← 0
                        RT2: PC ← PC + 1, IEN ← 0, R ← 0, SC ← 0

Memory-reference:
AND    D0T4: DR ← M[AR]
       D0T5: AC ← AC ∧ DR, SC ← 0
ADD    D1T4: DR ← M[AR]
       D1T5: AC ← AC + DR, E ← Cout, SC ← 0
LDA    D2T4: DR ← M[AR]
       D2T5: AC ← DR, SC ← 0
STA    D3T4: M[AR] ← AC, SC ← 0
BUN    D3T4: PC ← AR, SC ← 0
BSA    D5T4: M[AR] ← PC, AR ← AR + 1
       D5T5: PC ← AR, SC ← 0
ISZ    D6T4: DR ← M[AR]
       D6T5: DR ← DR + 1
       D6T6: M[AR] ← DR, if(DR = 0) then (PC ← PC + 1), SC ← 0

Register-reference:
D7I'T3 = r (common to all register-reference instructions)
IR(i) = Bi(i = 0,1,2,...,11)
r: SC ← 0
CLA rB11: AC ← 0
CLE rB10: E ← 0
CMA rB9:  AC ← AC
CME rB8:  E ← E
CIR rB7:  AC ← shr AC, AC(15) ← E, E ← AC(0)
CIL rB6:  AC ← shl AC, AC(0) ← E, E ← AC(15)
INC rB5:  AC ← AC + 1
SPA rB4:  If(AC(15) = 0) then (PC ← PC + 1)
SNA rB3:  If(AC(15) = 1) then (PC ← PC + 1)
SZA rB2:  If(AC = 0) then (PC ← PC + 1)
SZE rB1:  If(E = 0) then (PC ← PC + 1)
HLT rB0:  S ← 0

Input-output:
D7IT3 = p (common to all input-output instructions)
IR(i) = Bi(i = 6,7,8,9,10,11)
p: SC ← 0
INP pB11: AC(0-7) ← INPR, FGI ← 0
OUT pB10: OUTR ← AC(0-7), FGO ← 0
SKI pB9:  If(FGI = 1) then (PC ← PC + 1)
SKO pB8:  If(FGO = 1) then (PC ← PC + 1)
ION pB7:  IEN ← 1
IOF pB6:  IEN ← 0

The interrupt flip-flop R may be set at any time during the indirect or execute phases. Control returns to timing signal T0 after SC is cleared to 0. If R = 1, the computer goes through an interrupt cycle. If R = 0, the computer goes through an instruction cycle.

If the instruction is one of the memory-reference instructions, the computer first checks if there is an indirect address and then continues to execute the decoded instruction according to the flowchart of stored program organization.

If the instruction is one of the register-reference instructions, it is executed with one of the microoperations listed in the execution of Register-reference instruction. If it is an input-output instruction, it is executed with one of the microoperations listed in Input-Output Instruction. Instead of using a flowchart, we can describe the operation of the computer with a list of register transfer statements. This is done by accumulating all the control functions and microoperations in one table.