Instruction Cycle | Computer Architecture

Instruction Cycle in Computer Architecture – A program is defined as the collection of instructions to perform a specified operation. Program is normally stored in the consecutive memory locations. The program is executed in the computer by going through a cycle for each instruction.

Each instruction cycle in turn is subdivided into a sequence of subcycles or phases. The control unit is responsible for taking care of all possibilities at every phase of the instruction cycle.

Instruction Cycle

In a basic computer system, an instruction cycle consists of the following phases :

1. Instruction fetch
2. Decode the instruction
3. Calculate the effective address
4. Operand fetch
5. Instruction execution
6. Save the result

Instruction Fetch

The instruction fetch cycle starts with the loading of the instruction address from program counter (PC) to the address register (AR). The address register is connected to the address inputs of memory. It is necessary to transfer the address from program counter to address register during the clock transition. Now control unit generates the control signal, read, to place the instruction from memory unit to the instruction register (IR) with the next clock transition. At the same time, program counter is incremented by one. Now it is ready to fetch the next instruction from the memory.

Following micro operations shows the instruction fetch subcycle.

T0        : AR ← PC
read, T1  : IR ← M[AR], PC ← PC+1

Decode the instruction

Once the instruction gets fetched from the memory unit, the meaning of that instruction is calculated by the instruction decoder of the processor. In a 16-bit instruction, twelve least significant bits (0-11) represent the address of the operand, next three bits (12-14) represent the operation code (opcode) which is to be performed on the operands. The most significant bit (15) is transferred to a flip-flop I which indicates whether the address is direct or indirect.

Decoding of an instruction can be represented by the following micro operation.

T2 : D0,D1.......D7 ← Decode IR (12-14), AR ← IR (0-11), IF ← IR(15)

Calculate the effective address

An instruction is usually divided into parts and cach part has its own representation. One part of instruction code specifies the operation code, other part provides the address of operand and other remaining part indicates that the provided address is direct or indirect. If instruction shows the direct addressing scheme then the address in address field of the instruction is the effective address. For indirect addressing scheme, the effective address has to be calculated by the processor from the contents of address field of the instruction.

There are various addressing modes which are used in computer systems. Each addressing mode has its own way to calculate effective address of the operand. These are discussed in next section.

Operand Fetch

After calculating the effective address of the operand, the operand fetch subcycle is performed. If the operand is in main memory the processor performs the memory read operation. The number of memory read subcycles depends on the two factors : operand length and the memory word length. The control unit is responsible to keep a track of memory read cycles. If the operand is in a processor register, it will be read quickly compared to an operand from the memory.

Instraction Execution

The operation code (opcode), provided in instruction, specifies the exact micro operations in sequence to perform during the instruction execution. The execution process is controlled by the control unit of the computer. The number of micro operations performed, depends on the meaning of the instruction. It varies from no micro-operation to multiple micro operations.

Save the result

When the instruction execution is completed final result is stored. The result may be stored in the processor register or in memory unit. It depends on the nature of the instruction.