Serial Communication in Computer Architecture

Serial Communication in Computer Architecture – The input/output devices, DMA controller, and I/O processor use parallel communication. These devices transmit more than one bit of data at a time. A communication network may consist of any of a wide variety of devices, such as printers, display devices, and digital sensors.

Some of the devices can not handle more than one bit of data at a time. Such a type of devices use serial communication. However, computer systems in general do not communicate serially. Instead, the CPU has an interface that converts parallel data into serial and vice versa as per the requirement. There are two common modes of serial communication.

1. Asynchronous Serial Communication
2. Synchronous Serial Communication

Asynchronous Serial Communication

This mode is used to interact with the I/O devices that do not share a common clock, and synchronisation is required for data transfer. In order to synchronise two devices, there must be an agreement on several transmission parameters like speed of data transfer, format of data transfer, etc. Not agreeing on transmission parameters will cause data to be lost or corrupted.

One of the transmission parameters is the speed of data transfer. It is represented by the number of bits per second or bps. It is also known as the baud rate of the system. Before transmitting the data, the computer system must ensure that the I/O device is ready to accept data at the transmitting speed. 

Another parameter of transmission is the data transfer format. In asynchronous serial communication mode, for the receiving device to recognise when a transmission is occurring, when to read a bit of data, when the transmission is ending, and when the transmission line is idle i.e No data is being transmitted. For these reasons, the data transfer format must be the same. To indicate the start of data pansmission start bits are added to the original data. In the same way, end bits are generally added to the original data to indicate the end of data transfer. Generally, 1 start bit and 1, 1/2 or 2 stop bits are used; a parity bit may also be transmitted with data in addition to start and stop bits to detect errors in received data. The image shows an example of two-byte data transmission.

Transmission of numeric data using asynchronous serial communication mode is a simple process, but transmission of character data requires a bit of translation. Each character must be encoded as a unique binary value in such a way that both the sender and receiver can recognise it. There are several standards existing for the encoding of characters. Most commonly used is ASCII (American Standard Code for Information Interchange). In addition to this, there are other standards for representing characters, such as Unicode. It is used by the Java programming language.

Synchronous Serial Communication

This mode of serial communication improves the transmission performance by reducing the overhead bits, which are generally introduced in asynchronous serial communication. Instead of sending a start and stop bit for each data word, it concatenates several data words into a single data block. It also adds a few pieces of information in front of and behind the data block. Now the complete data block is named as a frame. However, the additional information represents overhead, but normally at a lower percentage than the overhead associated with asynchronous serial transmission.

A few additional pieces of information may be added to the data frame to detect the errors in transmission. In synchronous serial communication, the cyclic redundancy check (CRC) is used for this purpose, as a parity bit is used in asynchronous serial communication. A common synchronous serial communication standard, the High-Level Data Link Control (HDLC), is shown in the image below. In this, the leading flag and the trailing flag are used to indicate the start and end of the frame, respectively. The address and control fields specify the address of the destination and the function of the frame. The CRC is used to detect errors so that correct information may reach the destination.

The efficiency of a transmission is determined by calculating the percentage overhead. For example, if a frame consists of 512 bits of data, an 8-bit leading flag, an 8-bit address, an 8-bit control, a 16-bit CRC andan 8-bit trailing flag, then 48 bits (8+8+8+16+8=48-bits) are overhead bits. In this case percentage overhead will be 8.57%, (48/(48+512))×100%. Lowering the overhead percentage will result in higher performance of the transmission.

Universal Asynchronous Receiver/Transmitter (UART)

Asynchronous serial communication is a common method of communication. A few special ICs are designed by manufacturers with common functions to perform serial communication and relieve the CPU from this task. These special ICs are called universal asynchronous receivers/transmitters (UARTS). 

The image below shows the UART just as another parallel I/O device and interfaces with it accordingly. The UART can transmit (output) and receive (input) data serially. It can interact with serial interfacing devices. The UART exchanges data with the help of a modem (modulation + demodulation). 

The UART has several internal registers, just as in the DMA controller. A typical UART contains registers to hold transmitted and received data, a control register and a status register, all of which are accessible to the CPU.