Direct Memory Access in Computer Architecture

Direct Memory Access in Computer Architecture – Direct Memory Access (DMA) is an input/output technique commonly used for high-speed data transfer between memory and an I/O device. In this way, the limitation of other techniques like programmed I/O and interrupt I/O may be overcome. When a large amount of data is to be moved from system memory to an I/O device or vice versa, the DMA is an efficient technique.

What is Direct Memory Access?

In general, when a data transfer occurs, the processor gets engaged in managing the I/O transfer, and several instructions must be executed for each I/O transfer. In such cases, the data transfer between memory and the I/O device is limited by the speed ofthe processor. Therefore, removing the processor from the path and allowing the I/O device to manage the memory buses directly would improve the speed of data transfer. This technique is called direct memory access (DMA). The basic DMA technique is shown in the figure below. The device that controls the DMA is named the DMA controller.

Direct Memory Access Controller

Direct memory access involves an additional module on the system bus to control the whole DMA process. This module is called the DMA controller. It is capable of behaving as the processor by taking over the control of the system buses from the processor. It is a must to transfer data to and from memory over the system bus. Due to this, it must be taken care of by the DMA controller that uses the buses only when the processor does not need them, or it must force the processor to suspend the operation temporarily. The second technique is known as cycle stealing because the DMA controller, in effect, steals a bus cycle. A typical DMA controller block diagram is shown in the image below. 

The DMA controller contains various registers for its operation. The data/word count register provides the number of data/words that must be transferred. The data register is used to store data temporarily in the DMA controller. It accepts data from the data bus and behaves as a data bus buffer. The address register and address lines are used for direct communication with memory. The control logic is another block in the DMA controller that plays an important role in controlling the whole DMA operation. 

DMA operation is performed with I/O devices through the handshaking process. The DMA controller communicates with the processor through the data, address and control bus. The DMA controller is activated through the control line ‘DMA select’. The registers in the DMA controller are selected by the register select control line. The read and write inputs are bidirectional and used to activate the respective reading and writing operations. When the bus grant signal is low, it indicates, processor is using the system buses and if it is high, meaning that the processor has released the system buses for DMA operation. The interrupt signal is generated by the DMA control to indicate the processor that the DMA operation has been completed.

DMA Function

When the I/O device wants to access the system memory directly, it sends a request (DMA request) to the DMA controller. In response to this, the DMA controller sends a bus request to the processor to release the buses for DMA operation. If the processor is not using the system buses, it initialises the DMA controller by writing the starting address of the memory block where data is available (for reading) or where data is to be stored (for writing) and the word count. The processor also specifies the mode of transfer, such as read or write. Then the processor releases the system buses and informs the DMA controller through the bus grant signal. The DMA controller then puts the current value of its address register into the address bus, initiates a read or write signal and sends a DMA acknowledgement to the I/O device. 

The read and write signals are bidirectional. Till the buses are granted to the DMA controller, the read and write signals are controlled by the processor and input signals to the DMA controller. The processor uses these signals to read or write in the DMA registers. Once the processor grants the buses to the DMA controller, the read and write signals become output signals and are also controlled by the DMA controller. When an I/O device receives a DMA acknowledgement, it puts a word in the data bus (for write) or receives a word from the data bus (for read). Thus, the DMA controls the read or write operations and supplies the address for the memory.

For each data that is transferred, the address register is incremented, and the word count register is decremented. If the word count does not reach zero, the DMA controller again checks the DMA request line from the I/O device. If this is an active DMA operation for next word will continue. If the word count reaches zero, the DMA controller stops any further transfer and removes its bus request. It also informs the processor of the termination by means of an interrupt.

Note: A DMA controller may have more than one channel. In this case, each channel has a request and acknowledgement pair of control signals that are connected to separate 10 devices. Each channel also has its own address register and data word count register. 

Modes of Data Transfer

DMA controller operates in two modes for data transfer between I/O devices and system memory. These two modes are as follows: 

1. Slave Mode 
2. Master Mode 

(a) Slave Mode: In this mode, the DMA controller is treated as a peripheral. The following tasks are performed in this mode.

1. The processor selects the DMA controller through the DMA select signal 
2. The processor initialises the DMA controller by writing the starting memory address and word count for data transfer. 
3. Read and write signals are input signals to the DMA controller

(b) Master Mode: After initialisation, the DMA controller in master mode keeps checking for a DMA request, and the following tasks are performed in data transfer.

1. When the I/O device is ready for data transfer, it sends a signal to the DMA request. 
2. The DMA controller sends a bus request to the processor.
3. In the next cycle, the processor releases the buses and sends a bus grant signal to the DMA controller. 
4. After receiving the bus grant, the DMA controller places the address on the address lines and generates the signal DMA acknowledgement. 
5. Now DMA controller continues the data transfer by asserting the necessary control signal (read or write).
6. At the end of datat transfer, the DMA controller assertsan interrupt signal that can be used to inform the peripheral or processor that data transfer is completed.