Bus Architecture in Computer Architecture

Bus Architecture in Computer Architecture – Any processor-based system contains many components like memory, input-output, etc. There are many registers in a computer. To communicate the data between various components, a path is required.

There will be an excessive number of wires if separate lines are used between each register and all other registers in the system. Therefore, a common bus system is more preferable. A bus architecture consists of a collection of common lines, one for each bit of a register, through which binary information is transferred one bit at a time. To select a particular register, control lines are used. There are two methods to design the common bus system in a computer.

Bus Architecture

1. Multiplexer based
2. Tri-state buffer-based

Multiplexer-Based Bus Architecture

One efficient way of constructing a common bus system is using multiplexers. There are many registers in computer architecture. Multiplexers are simply used to select the source register and place the binary information on the bus. The bus architecture with four registers is shown in the figure below.

The bus consists of four 4:1 multiplexers. There are two selection lines, S₁ and S₀, which are used to select the particular input line of multiplexers.

The above figure shows that the bits in the same significant position in each register are connected to the data inputs of one multiplexer to form one line of the bus. For example, if selection lines S₁S₀ = 0 0, then I₀, the input of each multiplexer, reaches the output line.

It means the output of MUXO will be A₀, the output of MUX1 will be A₁, the output of MUX2 will be A₂, and the output of MUX3 will be A₃. In this way, the complete information from register A will move into the common bus. The function table for the common bus architecture shown in the above figure is given in the table below.

Selection lines S1	Selection lines S0	Register selected
S1	S0
0	0	Register A
0	1	Register B
1	0	Register C
1	1	Register D

The writing into one of many registers from the bus can also be achieved by connecting the bus lines to the inputs of all destination registers and activating the load control of the particular destination register selected.

Note: A bus system will multiplex k registers of n-bits each produce an n-line common bus. For such a bus system, a number of multiplexers with k: 1 size are required.

Example 2.1: How many multiplexers are required to design a common bus architecture using a multiplexer? Also, find the size of each multiplexer. There are a total of 32 registers of 8 bits.

Solution: Number of multiplexers = number of bits
=8
Therefore total of 8 multiplexers are required
Size of multiplexer number of registers: 1
=32:1
Hence, the size of each multiplexer required is 32:1.

Tri-state Buffer-Based Bus Architecture

A tri-state buffer can also be used to construct a common bus system instead of a multiplexer. A tri-state buffer is characterized by the presence of three signal values: 0, 1, and high impedance (z). Two of the states are signals equivalent to logic 1 and logic 0, as in conventional logic gates. The third state (high impedance) state behaves like an open circuit, i.e., electrically disconnected from all voltage sources.

The symbol of a tri-state buffer is shown in the figure below. The symbol shows there are two input signals

1. Normal input and
2. Control input.

The control input signal makes it distinguishable from the normal buffer. When the control signal (active high) goes high, the buffer enables and behaves like any conventional buffer.

Whereas when the control signal goes low, the buffer goes to a high state and behaves as if there is no electrical connection between the input and output of the buffer. This is a special feature that is not available in conventional buffers. Because of this feature, a large number of tri-state buffer outputs can be connected with wires to form a common bus line without endangering loading effects.

Control Input	Normal Input	Output
0	0	High Impedance
0	1	High Impedance
1	0	0
1	1	1

The common bus architecture using a tri-state buffer is shown in the figure below. This common bus system for one bus line is designed with the help of one decoder and four tri-state buffers. The output of the decoder is used as the control input of the buffers.

The decoder activates one of the buffers through the control input, and the normal input of that buffer reaches the output of the buffer. The other three buffers remain in a high impedance state and behave as electrically disconnected. The outputs of all four buffers are connected together to form a single bus line.

The above figure also shows an additional input “E” (enable input) to the decoder. When the enable input of the decoder is low (E=0), all of its four outputs are 0, and the bus line is in the high impedance state because all four buffers are disabled. When the enable input is active, one of the tri-state buffers will be active, depending on the binary value in the selection inputs of the decoder. The function table for bus architecture using a tri-state buffer is given in below.

Enable	Selection lines	Selection lines	Register selected
E	S1	S0
0	x	x	High Impedance
1	0	0	Register A
1	0	1	Register B
1	1	0	Register C
1	1	1	Register D

In common bus architecture using tri-state bus is used to ensure that no more than one control input is active at any given time.

Note: To design a common bus using a tri-state buffer for k registers of n bits, n circuits with mimber buffer are required.

Comparison Between Various Common Bus Architectures

In the previous sections, two of the common bus architectures using a multiplexer and tri-state buffer were discussed. The basic limitation of the common bus architecture using a multiplexer is the fan-in and fan-out limit. The common bus architecture using a tri-state buffer greatly increases these limits and allows a large number of devices to be attached to the same line.

The tri-state buffer bus architecture also has another advantage over the multiplexer bus architecture that it supports bidirectional transmission over the bus by allowing the bus connection to serve as an input port and output port at different times.

However, a careful investigation will show that the combination of decoder and tri-state buffers is another way of constructing a multiplexer for better performance.

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