Arithmetic Pipeline in Computer Architecture

Arithmetic Pipeline in Computer Architecture – The simplest structure of a pipeline may be considered as a combination of registers and combinational circuits. The register holds the data, and the combinational circuit performs the sub-operations in that particular segment.

Arithmetic Pipeline

In Computer Architecture arithmetic pipeline is generally implemented in very high-speed computers to implement the complex arithmetic functions. This is used to perform floating-point operations, multiplication of fixed-point numbers, and similar computations.

The arithmetic pipeline structure can be illustrated with an example. Suppose the desired operation is defined as

Fi = (Ai * Bi) + (Ci * Di) for i=1,2,.....5

To perform the above operation, each sub-operation is to be implemented in a segment within a pipeline. Each segment has one or two registers and a combinational circuit, as shown in the figure below. All the registers receive and store new data with every clock pulse. There are seven registers with two multipliers and one adder combinational circuit.

Three segments may be considered as shown in the above figure. All these segments perform their functions separately. Once segment 1 completes its operation, it passes its output to segment 2, and segment 2 passes its output to segment 3 after completing its own operation. The table below shows the sub-operations performed in each segment.

Segment	Register Transfer Language	Function
Segment 1	R1 ← Ai, R2 ← Bi, R3 ← Ci, R4 ← Di	Input data
Segment 2	R5 ← R1 * R2, R6 ← R3 * R4	Multiplication
Segment 3	R7 ← R5 + R6	Addition

All seven registers (R₁ to R₇) are loaded with new data on occurence of a clock pulse. The effect of each clock pulse is given table below.

Clock Plse	Seg ment1 R1	Seg ment1 R2	Seg ment1 R3	Seg ment1 R4	Seg ment2 R5	Seg ment2 R6	Seg ment3 R7
1	A1	B1	C1	D1	–	–	–
2	A2	B2	C2	D2	A1 * B1	C1 * D1	–
3	A3	B3	C3	D3	A2 * B2	C2 * D2	A1*B1 + C1*D1
4	A4	B4	C4	D4	A3 * B3	C3 * D3	A2*B2 + C2*D2
5	A5	B5	C5	D5	A4* B4	C4 * D4	A3*B3 + C3*D3
6	–	–	–		A5 * B5	C5 * D5	A4*B4 + C4*D4
7	–	–	–		–	–	A5*B5 + C5*D5

The above table indicates that the first clock pulse transfers A1, B1, C1, and D1 into registers R1, R2, R3, and R4. The second clock pulse transfers the product of R1 and R2 into R5 and the product of R3 and R4 into R6. The same clock pulse transfer A2, B2, C2 and D2 into R1, R2, R3 and R4. The third clock pulse operates on all three segments simultaneously.

It places A3, B3, C3, and D3 into R1, R2, R3, and R4, transfers the product of R1 and R2 into R5 and the product of R3 and R4 into R6, and places the sum of R5 and R6 into R7. These sub-operations show that three clock pulses are taken to fill the pipe and to retrieve the first output from R7. After that, each clock produces a new output and moves the data one step down in the pipeline. It is important to note that when no input data are available, the clock must continue until the last output emerges from the pipeline.

---

Related Questions and Answers