Array Multiplier in Computer Architecture YASH PAL, January 28, 2026January 30, 2026 Array Multiplier in Computer Architecture – The multiplication of two binary numbers can be performed with one micro operation by means of a combinational circuit. This combinational circuit produces the product bits all at once. This circuit is named the array multiplier. This is a fast way of multiplying two numbers. However, it takes time for the signal to propagate through a number of gates that form the array multiplier. An array multiplier requires a large number of gates and, therefore not an economical solution for multiplication. Multiplication of two 4-bit binary numbers is carried out by multiplying each bit of the multiplication as a partial product and summing all the partial products. Let the multiplicand be A3A2A1A0, and the multiplier be B3B2B1B0. Now perform the multiplication as follows: A3 A2 A1 A0 x B3 B2 B1 B0 _______________________________________ A3B0 A2B0 A1B0 A0B0 ← Row 1 A3B1 A2B1 A1B1 A0B1 - ← Row 2 A3B2 A2B2 A1B2 A0B2 - - ← Row 3 M3B3 A2B3 A1B3 A0B3 - - - ← Row 4 _______________________________________ M7 M6 M5 M4 M3 M2 M1 M0 _______________________________________ Each bit (starting from the LSB) of the multiplier is multiplied by each bit of the multiplicand, as shown in each row. Now, corresponding bits are added, first Row 1 and Row 2 are added, and a partial sum is obtained. Next, Row 3 is added to the partial sum and so on. Bits Ai, Bi, represent the AND operation. So Row 1 and Row 2 are added by a 4-bit binary adder, and the partial sum is obtained. Now Row 3 is added to the partial sum, and the next partial sum is finally obtained. Row 4 is added to the previous partial sum by a 4-bit adder, and the final result is obtained. A3 A2 A1 A0 x B3 B2 B1 B0 _______________________________________ 0 A3B0 A2B0 A1B0 A0B0 A3B1 A2B1 A1B1 A0B1 - _______________________________________ Cout P1S3 P1S2 P1S1 P1S0 A0B0 Partial sum _______________________________________ A3B2 A2B2 A1B2 A0B2 - - _______________________________________ Cout P2S3 P2S2 P2S1 P2S0 P1S0 A0B0 Partial sum _______________________________________ A3B3 A2B3 A1B3 A0B3 - - - _______________________________________ Cout P3S4 P3S2 P3S1 P3S0 P2S0 P1S0 A0B0 Final Result _______________________________________ M7 M6 M5 M4 M3 M2 M1 M0 The figure below shows an array multiplier for the multiplication of two 4-bit numbers. 4×4 bit array multiplier Computer System Architecture engineering subjects Computer System Architectureengineering subjects