Common Bus System | Computer Architecture

Common Bus System in Computer Architecture – The basic computer system has various registers, a memory unit, and a control unit. The information is transferred from one unit to another to complete the required operation. Therefore, a path must be provided between these units.

If separate lines are used to provide the path, the number of wires will be excessive in the system. A more efficient method for transferring information between different units of a computer system is a common bus system. A common bus can be constructed using a tri-state buffer or using multiplexer.

Common Bus System Architecture

A common bus system is used to transfer the information between different units of the computer system. The figure below shows the connections of registers and a memory unit of a computer system to a Common bus.

Note: This figure only shows the basic common bus system architecture. As clocks and other control signals are not shown in the above figure.

Working Principle of Common Bus System

The outputs of registers and memory units are connected to the common bus. In the same manner, the common bus is also connected to the inputs of each register and the data inputs of the memory.

Whenever a register wants to receive data from a common bus, one of the control signal load (LD) must be enabled. The particular register which is having load (LD) control signal enabled receives the data from the common bus during the next clock pulse. If two or more registers have the LD control signal enabled simultaneously, they may receive the same data from the common bus. The memory receives the contents of the common bus only when its write input is enabled.

The multiplexer is used to select a specific output for the common bus at any given time. There are three selection lines for the multiplexer. The binary values in these lines activate the specific output from the registers. The number along each output shows the decimal equivalent of the required binary selection. For example, the accumulator (AC) can place the output on the common bus if the selection lines contain 1002 (410)

As shown in the above figure, the input data and output data of the memory unit are connected to the common bus, and the memory can perform a reading or writing operation when the proper control signal (read or write).

However, the memory address is connected to AR only; this register must be used to specify the address of a register in the memory unit where the reading or writing operation is to be performed. This kind of bus architecture eliminates the requirement of a separate address bus. The memory unit can receive the data from any of the registers, and similarly, all the registers except the accumulator (AC) can receive the data from the memory unit directly.

In a common bus system, there is an arithmetic and logic unit. It has three inputs. One set of 16-bit input lines came from the output lines of the accumulator. This set can be used to perform the micro operations with the accumulator only, like shift AC and complement AC. Another set of 16-bit input lines comes from the data register (DR).

This set is used to perform micro operations which are having two operands, like addition. In such a case, one operand is stored in the accumulator and the other operand in the data register. A third set of 8-bit inputs comes from the input register (INPR). This set is used to communicate with the input device.

The input register (INPR) and output register (OUTR) are used to communicate with the I/O devices. The serial information from the input device is stored in the input register. It converts this serial information into parallel and transfers it to the arithmetic and logic unit.

Similarly, the serial information for the output device is stored into output register. The output register transfers the parallel information in a serial manner to the output device. These two registers communicate with I/O devices serially and with the accumulator in parallel.

---

Related Questions and Answers