Modes of Data Transfer in Computer Architecture

Modes of Transfer in Computer Architecture – Any computer system consists of three basic units. The first one is the central processing unit CPU), which processes the information received froin remaining two units. The second unit is the main memory unit where the results after processing are stored. The third unit components are secondary memory and input output devices. The interconnection between the three units is shown in the figure below.

The binary information received from an input device or secondary memory is usually stored in main memory for later processing. Similarly, the information transferred from the CPU to the output device or secondary memory is also stored in the main memory. Data transfer between the CPU and I/O devices may be handled in a variety of modes. Some modes use the CPU as an intermediate path; others transfer the data directly to and from the memory unit. There are three modes that are usually applied for a data transfer to and from I/O devices.

Modes of Transfer

1. Programmed I/O
2. Interrupt-Initiated I/O
3. Direct Memory Access (DMA) I/O

Programmed I/O

Program I/O data transfer is controlled by the CPU. It is a result of I/O instructions written in the program. Once the 1/0 is executed by the processor, the CPU places the address of the I/O device into the address bus and perform read/write operation by generating proper control signals. It means, in this mode of transfer, all input/output operations are executed under the direct control of the CPU.

When the CPU executes an input/output instruction, it assumes that the 1/0 device is ready to transfer the data. The I/O device must transfer data to and from the CPU within a specified time period. This process may lose the information if data is transferred from the CPU and the output device is not ready. To prevent the loss of information, the CPU must check the status of external devices before transferring the data. This also eliminates the indefinite waiting time for CPU Hence, the CPU performs the following steps in programmed I/O.

1. Check the status of the I/O device 
2. If the device is ready, perform the transfer; else, return to step (i)

The figure below shows the flow chart of programmed I/O transfer mode.

Interrupt-Initiated I/O

As shown in the above figure, in programmed I/O, the CPU continuously checks the status of the I/O device until it gets ready for data transfer. This is a time-consuming process since it keeps the processor busy unnecessarily. This situation can be avoided by using the concept of an interrupt. In accordance with this, the I/O device issues a specific signal that indicates to the CPU that the I/O device is ready for data transfer. In the meantime, the CPU can execute another program. The request signal generated by the I/O device is known as an interrupt signal, and this process of data transfer is known as interrupt initiated 1/0 transfer mode. The advantage of this transfer mode is that it makes the system faster. The limitation of this is that it makes the system architecture complex.

Direct Memory Access (DMA) I/O

DMA I/O transfer mode is commonly used for high-speed data transfer, for example, data transfer between memory and I/O devices. In programmed I/O and interrupt initiated 1/0, data transfer is relatively slow because cach instruction needs to be fetched and executed in DMA. The CPU releases control of the system bus to a device called the DMA controller. The DMA controller manages data transfer between memory and an I/O device. It bypasses the role of the processor. The DMA I/O is initiated by the CPU by transferring the starting address and the number of data words needed to be transferred, and then the CPU proceeds to execute other programs DMA controller may have more than one channel. In this case, each channel has its own address register and data word count register within the DMA controller. A priority may be established for the number of channels. High-priority channels are serviced first, then channels with lower priority.