RISC and CISC In Computer Architecture

RISC and CISC in Computer Architecture – In computer architecture, Reduced Instruction Set Computer (RISC) and Complex Instruction Set Computer (CISC) are the instructions set computer. where a computer with a large number of instructions is classified as a complex instruction set computer (CISC), and A computer with fewer instructions is defined as a reduced instruction set computer.

Reduced Instruction Set Computer (RISC)

A reduced instruction set computer (RISC) is a computer that uses a central processing unit (CPU) that implements the processor design principle of simplified instructions. To date, RISC is the most efficient CPU architecture technology. Reduced instruction actually means that the amount of work done by each instruction is reduced in terms of the number of cycles, at most only a single data memory cycle, and makes them cheaper to design. In which dozens of cycles are required prior to completing the entire instruction. This results in faster processing.

The most basic RISC feature is a processor with a small core logic that allows engineers to increase the register set and increase internal parallelism.

Examples of RISC processors:

• IBM RS6000, MC88100
• DEC’s Alpha 21064, 21164, and 21264 processors
• Alpha. ARC, ARM, AVR, MIPS, PA-RISC, PIC, Power Architecture, and SPARC.

Characteristic of RISC –

• Simpler instruction, hence simple instruction decoding
• Instructions come under the size of one word.
• Instructions take a single clock cycle to get executed.
• More number of general purpose register.
• RISC permits any register to be used in any context.
• Simple Addressing Modes.
• Fewer data types.
• In RISC, more RAM is required to store assembly-level instructions.
• Pipelining can be achieved.
• RISC helps and supports a few simple data types and synthesizes complex data types.
• Used fixed-length instructions for pipelining.
• Reduced instructions need a lesser number of transistors.

The Advantages of RISC architecture:

• RISC architecture has a set of instructions, so high-level language compilers can produce more efficient code.
• It allows freedom in using the space on microprocessors because of its simplicity.
• Many RISC processors use the registers for passing arguments and holding local variables.
• RISC functions use only a few parameters, and the RISC processors cannot use the call instructions; therefore, use a fixed-length instruction, which is easy to pipeline.
• The speed of the operation can be maximized, and the execution time can be minimized. Very less number of instructional formats, a few instructions, and a few addressing modes are needed

The Disadvantages of RISC architecture:

• Mostly, the performance of the RISC processors depends on the programmer or compiler, as the knowledge of the compiler plays a vital role while changing the CISC code to a RISC code.
• While rearranging the CISC code to a RISC code, termed as a code expansion, will increase the size. And, the quality of this code expansion will again depend on the compiler, and also on the machine’s instruction set.
• The first-level cache of the RISC processors is also a disadvantage of the RISC, in which these processors have large memory caches on the chip itself. For feeding the instructions, they require very fast memory systems.

Complex Instruction Set Computer (CISC)

A complex instruction set computer is a computer where single instructions can perform numerous low-level operations, like a load from memory, an arithmetic operation, and a memory store, or are accomplished by multi-step processes or addressing modes in single instructions. As its name suggests, “Complex Instruction Set”, the CISC architecture is designed to decrease the memory cost. Because the large programs need more storage, thus increasing the memory cost, and large memory becomes more expensive. To solve these problems, the number of instructions per program can be reduced by embedding the number of operations in a single instruction, thereby making the instructions more complex.

Examples of CISC PROCESSORS:

System/360, VAX, PDP-11. Motorola 68000 family, AMD, and Intel x86 CPUs.

• IBM 370/168 – It was introduced in the year 1970. CISC design is a 32-bit processor with four 64-bit floating-point registers.
• VAX 11/780 – CISC design is a 32-bit processor, and it supports a number of addressing modes and machine instructions which is from Digital Equipment Corporation.
• Intel 80486 – It was launched in the year 1989, and it is a CISC processor, which has instructions varying in length from 1 to 11, and it has 235 instructions.

The Performance Equation:

The following equation is commonly used for expressing a computer’s performance ability:

time/program = (time/cycle) x (cycles/instruction) x (instructions/program)

The CISC approach attempts to minimize the number of instructions per program, sacrificing the number of cycles per instruction. RISC does the opposite, reducing the cycles per instruction at the cost of the number of instructions per program.

Characteristic of CISC:

1. Complex instruction, hence complex instruction decoding.
2. Instructions are larger than one word size.
3. Instruction may take more than a single clock cycle to get executed.
4. A smaller number of general purpose register as operation get performed in memory itself.
5. Complex Addressing Modes.
6. More Data types.

Advantages of CISC architecture:

• Microprogramming is easy assembly language to implement, and less expensive than hardwiring a control unit.
• The ease of microcoding new instructions allowed designers to make CISC machines upwardly compatible:
• As each instruction became more accomplished, fewer instructions could be used to implement a given task.

Disadvantages of CISC architecture:

• The performance of the machine slows down because the amount of clock time taken by different instructions will be dissimilar.
• Only 20% of the existing instructions are used in a typical programming event, even though there are various specialized instructions in reality that are not even used frequently.
• The conditional codes are set by the CISC instructions as a side effect of each instruction, which takes time for this setting, and, as the subsequent instruction changes the condition code bits, the compiler has to examine the condition code bits before this happens.