Address Sequencing in Computer Architecture

Address Sequencing in Computer Architecture – Microinstructions are stored in control memory in groups, with each group specifying a routine. Each computer instruction has its own microprogram routine in control memory to generate the micro-operations that execute the instruction.

The hardware that controls the address sequencing of the control memory must be capable of sequencing the microinstructions within a routine and be able to branch from one routine to another. For address sequencing in a micro-program control unit, the control must undergo four steps during the execution of a single computer instruction.

The four steps of Address sequencing capabilities required in a control memory are:

1. Incrementing of the control address register.
2. Unconditional branch or conditional branch, depending on status bit conditions.
3. A mapping process from the bits of the instruction to an address for control memory.
4. A facility for subroutine call and return.

Step-1: Incrementing of the control address register.

• An initial address is loaded into the control address register when power is turned on in the computer.
• This address is usually the address of the first microinstruction that activates the instruction fetch routine.
• The fetch routine may be sequenced by incrementing the control address register through the rest of its microinstructions.
• At the end of the fetch routine, the instruction is in the instruction register of the computer.

Step-2: Unconditional branch or conditional branch, depending on status bit conditions.

• The control memory next must go through the routine that determines the effective address of the operand.
• A machine instruction may have bits that specify various addressing modes, such as indirect address and index registers.
• The effective address computation routine in control memory can be reached through a branch microinstruction, which is conditioned on the status of the mode bits of the instruction.
• When the effective address computation routine is completed, the address of the operand is available in the memory address register.

Step-3: A mapping process from the bits of the instruction to an address for control memory.

• The next step is to generate the microoperations that execute the instruction fetched from memory.
• The microoperation steps to be generated in processor registers depend on the operation code part of the instruction.
• Each instruction has its own micro-program routine stored in a given location of control memory.
• The transformation from the instruction code bits to an address in control memory where the routine is located is referred to as a mapping process.
• A mapping procedure is a rule that transforms the instruction code into a control memory address.

Step-4: A facility for subroutine call and return.

• Once the required routine is reached, the microinstructions that execute the instruction may be sequenced by incrementing the control address register.
• Micro-programs that employ subroutines will require an external register for storing the return address.
• Return addresses cannot be stored in ROM because the unit has no writing capability.
• When the execution of the instruction is completed, control must return to the fetch routine.
• This is accomplished by executing an unconditional branch microinstruction to the first address of the fetch routine.

Selection of Address for Control Memory

The figure given below shows a block diagram of a control memory and the associated hardware needed for selecting the next microinstruction address. The microinstruction in control memory contains a set of bits to initiate microoperations in computer registers and other bits to specify the method by which the next address is obtained.

The diagram shows four different paths from which the control address register (CAR) receives the address. The incrementer increments the content of the control address register by one to select the next microinstruction in sequence. Branching is achieved by specifying the branch address in one of the fields of the microinstruction.

Conditional branching is obtained by using part of the microinstruction to select a specific status bit in order to determine its condition. An external address is transferred into control memory via a mapping logic circuit. The return address for a subroutine is stored in a special register whose value is then used when the microprogram wishes to return from the subroutine.

The branch logic of the above Figure provides decision-making capabilities in the control unit. The status conditions are special bits in the system that provide parameter information such as the carry-out of an adder, the sign bit of a number, the mode bits of an instruction, and input or output status conditions.

The status bits, together with the field in the microinstruction that specifies a branch address, control the conditional branch decisions generated in the branch logic. Al output in the multiplexer generates a control signal to transfer the branch address from the microinstruction into the control address register.

A 0 output in the multiplexer causes the address register to be incremented.

Mapping of an Instruction

A special type of branch exists when a microinstruction specifies a branch to the first word in control memory, where a microprogram routine for an instruction is located. The status bits for this type of branch are the bits in the operation code part of the instruction.