Interprocessor Arbitration in Computer Architecture

Interprocessor Arbitration in Computer Architecture – A computer system needs buses to facilitate the transfer of information between its various components. For example, even in a uniprocessor system, if the CPU has to access a memory location, it sends the address of the memory location on the address bus.

This address activates a memory chip. The CPU then sends a red signal through the control bus, in response to which the memory puts the data on the address bus. This address activates a memory chip. The CPU then sends a read signal through the control bus, in response to which the memory puts the data on the data bus. Similarly, in a multiprocessor system, if any processor has to read a memory location from the shared areas, it follows a similar routine.

There are buses that transfer data between the CPUs and memory. These are called memory buses. An I/O bus is used to transfer data to and from input and output devices. A bus that connects major components in a multiprocessor system, such as CPUs, I/Os, and memory, is called the system bus. A processor, in a multiprocessor system, requests access to a component through the system bus.

In case no processor is accessing the bus at that time, it is given control of the bus immediately. If there is a second processor utilizing the bus, then this processor has to wait for the bus to be freed. If at any time, there is a request for the services of the bus by more than one processor, then the arbitration is performed to resolve the conflict. A bus controller is placed between the local bus and the system bus to handle this.

Types of Bus Arbitration

There are two types of bus arbitration to achieve the Interprocessor Arbitration, namely

1. Centralized Arbitration.
2. Distributed Arbitration.

Centralized Arbitration

Only a single bus arbiter performs the required arbitration, and it can be either a processor or a separate DMS controller.

There are three arbitration schemes that run on centralized arbitration.

Daisy Chaining

It is a simple and cheaper method where all the masters use the same line for making bus requests. During any bus cycle, the bus master may be any device – the processor or any DMA controller unit, connected to the bus.

Advantages

• Simplicity and Scalability
• The user can add more devices anywhere along the chain, up to a certain maximum value.
• Fewer control lines.

Disadvantages

• The value of priority assigned to a device depends on the position of the master bus.
• Propagation delay arises in this method.
• If one device fails, then the entire system will stop working

Polling Method

In this method, the devices are assigned unique priorities and compete to access the bus, but the priorities are dynamically changed to give every device an opportunity to access the bus. The controller is used to generate address lines for the master. For example, if there are 8 masters connected in a system, at least 3 address lines are required.

Advantages

• This method does not favor any particular device or processor.
• The method is also quite simple.
• If one device fails, then the entire system will not stop working.
• Priority flexible.

Disadvantages

• Adding bus masters is different as it increases the number of address lines of the circuit.

Fixed priority or Independent Request

In this method, the bus control passes from one device to another only through the centralized bus arbiter. Each bus has its own bus request and a grant. The built-in priority decoder selects the highest priority requests and asserts the system.

Advantages

• This method generates a fast response.
• Bus arbitration is fast.
• Speed is independent of the number of devices connected.

Disadvantages

• Hardware cost is high as a large number of control lines are required.
• Connecting a large number of bus masters is difficult.

Distributed Arbitration

• Here, all the devices participate in the selection of the next bus master.
• Each device on the bus is assigned a 4-bit identification number.
• When one or more devices request control of the bus, they assert the start arbitration signal and place their 4-bit identification numbers on arbitration lines through ARB3.
• Each device compares the code and changes its bit position accordingly.
• It does so by placing a 0 at the input of their drive.
• The distributed arbitration is highly reliable because the bus operations are not dependent on devices.