Design of A Basic Computer | Computer Architecture

Design of Basic Computer in Computer Architecture – To design a Basic computer we need to put all of these components together in one system. As shown in below figure. a basic computer which is having no interrupt facility, consists of the following hardware components.

1. Memory Unit
2. Register Array
3. Control Unit
4. Arithmetic and Logic Unit
5. Common Bus System

Basic Computer Design Components

Memory Unit

Let us consider for a basic computer system a memory size of 4k x16 bits is sufficient. In such memory, there are 4096 words with size of each word 16 bits. Since there are 4k (2¹²) words, 12-bits are required to specify the address of an operand in memory. In the simplest from of computer organization, instructions are stored in one section of the memory and data in another section.

Other units of basic computer has to ways to access the memory. It may read a location by transferring a copy of the memory cell to itself. Alternately, other unit may write to a memory location. A write operation transfers a new data to the memory location overwriting its previous contents. Reading and writing operation on memory unit can be performed only occurring of proper control signal. For reading, control signal : read and for writing control signal : write is generated by the control unit.

Below figure shows the basic architecture of a memory unit (size 4k× 16 bits) with two control signals read and write.

Register Array

In a basic computer, a processor register is a small amount of storage that is available to the processor. The computer hardware contains various registers like address register (AR), Program counter (PC), data register (DR), accumulator (AC), instruction register (IR), temporary register (TR), output register (OUTR), input register (INPR) and sequence counter (SC). These registers are having their own functions. Below table gives a brief description of cach register used in basic computer architecture.

Register Name	Symbol	Number of bits	Description
Address Register	AR	12	Holds address of memory
Program Counter	PC	12	Holds address of instruction
Data Register	DR	16	Holds memory operand
Accumulator	AC	16	Processor register
Instruction Register	IR	16	Holds temporary data
Temporary Register	TR	15	Holds temporary data
Output Register	OUTR	8	Holds output data
Input Register	INPR	8	Holds input data
Sequence counter	SC	12	Holds sequence counter value

There are three flip-flop (I, S and E) which are used to store various conditions of the processor operations. The addressing mode of an instruction is designated by the I flip-flop. The flip-flop is 0 (reset) for a direct address and 1 (set) for an indirect address. In other words, if the I flip-flop is reset, then the current instruction is recognized as a direct address instruction and if I flip-flop is set then as indirect address instruction.

The S flip-flop represents the sign of the result after performing an arithmetic or logic operation. This flip-flop is a replica of most significant bit of the result. This flip-flop shows correct sign if sign-magnitude representation is used while performing the operation.

When an arithmetic operation is performed, the result is transferred to the accumulator. If result is more than accumulator size then it is transferred to flip-flop E. For example, the contents of data register (DR) and accumulator (AC) are added. The result of the addition will be transferred to accumulator and the end carry out of the addition will be transferred to fliр-flop Е.

Control Unit

The control unit is the unit which directs the other units to perform the specific task. The control unit of a basic computer consists of two decoders, a sequence counter and a number of control logic gates. Below figure shows the control unit of basic computer.

An instruction read from memory unit is placed in the instruction register (IR) as shown in above figure. The operation code (opcode) bits (12-14) are decoded by a 3 x 8 decoder. The outputs of decoder are designated by D₀ to D₇. In the same manner, output of the sequence counter are decoded by 4 x 16 decoder. The output of this decoder are designated by T₀, to T₁₅.

The sequence counter has three input signals. Increment, clear and clock. Usually, the sequence of timing signals out of 4 x 16 decoder. The sequence counter is incremented with every positive clock transition, unless it is cleared by the CLR input. If sequence counter is not cleared, the timing signals continues with T₀ T₁ ……… up to T₁₅, and back to T₀.

The control logic gates block has various inputs : output from two decoders, the I flip-flop, bits 0 through 11 of instruction register (IR) and other inputs. The other inputs to the control logic are contents of accumulator, data register and values of other flip-flops.

The output of the control logic circuit are –

1. Signal to control the inputs of various registers
2. Signals to control writing and reading operation of memory unit
3. Signals to set, clear or complements of flip-flop
4. Signals for selection lines to select a register for the common bus
5. Signals to control arithmetic and logic unit.

Arithmetic and Logic Unit

The arithmetic and logic unit (ALU) performs arithmetic and logic operations on the contents of internal registers. It performs various operations like addition, subtraction, multiplication, logical AND etc. In few applications, the shift operation is also desired. For such cases, a shifter circuit may be added to this unit. Now this unit is named as arithmetic logic shift unit. For more knowledge about arithmetic, Logic and shift micro operations read the below articles.

• Number System Arithmetic
• Micro operations

Common Bus System

A common bus in a basic computer provides a common path between its various units. A 16-b common bus is already shown in this article – Common bus system in computer architecture. bus structure consists of a set of common lines, one for each bit of a register, through which binary information is transferred one at a time. Control signals generated by the control unit, determine which register is selected by the bus during each particular register transfer.