RISC and CISC Characteristics and Differences | Computer Architecture

RISC and CISC Characteristics and Differences – Design of an instruction set is an important aspect of computer architecture. In the early days of computer generations, small and simple instruction sets were used to reduce the hardware requirements.

With the advent of integrated circuits (ICs), computer instructions tended to increase both in number and complexity. Nowadays, the computer architecture evolves a larger instruction set, more addressing modes, more computational power of the individual instructions, and more specialized registers. A computer with a large number of instructions is classified as a Complex Instruction Set Computer (CISC).

Some of the instructions provided by CISC processors are so complex that many compilers simply do not attempt to use them. So adding these instructions to the instruction set affects the efficiency and the cost of the processor. Therefore, the computers with fewer instructions are recommended for faster execution. This type of computer is classified as a Reduced Instruction Set Computer (RISC).

RISC and CISC

Complex Instruction Set Computer (CISC)

In earlier cases, the complex operations are directly provided in the form of a processor instruction due to the small hardware cost. This results in an increase of internal hardware of the processor but provides a single instruction for complex operations.

While using the CISC architecture, the high-level program can easily be transformed into machine level by a compiler. Typical CISC architecture contains 100 to 200 instructions in its instruction set. The formats of instructions are also variable to accommodate flexibility, which makes instructions vary in terms of the clock cycles needed to execute them. Examples of CISC architecture are the Digital Equipment Corporation VAX computer and the IBM 370 computer.

The major properties of CISC architecture are as follows:

1. Large instruction set.
2. Variable-length instruction.
3. Specialized instructions that are used infrequently.
4. A large variety of addressing modes.
5. Microprogrammed control unit.
6. Instructions that manipulate operands directly in memory.

Reduced Instruction Set Computer (RISC)

The RISC architecture supports only commonly used instructions, which reduces the complexity of the control unit of the processor and increases execution speed. Most of the instructions perform operations on register contents. The memory access is limited to only load and store instructions. Few addressing modes are supported by the RISC architecture. The instruction format for the RISC processor is simple, which makes decoding faster.

The major properties of RISC architecture are as follows:

1. Small instruction set.
2. Few addressing modes.
3. Fixed-length and easily decoded instruction format.
4. Single-cycle instruction execution.
5. Hardwired control unit.
6. Memory access is limited to load and store instructions only.
7. Register-based execution.
8. Highly pipelined superscalar architecture.
9. Use of register windows.

The Berkeley RISC-I is one of the first projects to show the advantage of RISC architecture conducted at the University of California, Berkley.

CISC Versus RISC Difference

There is still considerable controversy among experts about which architecture is better. Some say that the RISC is cheaper and faster; therefore, this is the architecture of the future.

Others say that by making the hardware simpler, RISC puts a great burden on the software. Software needs become more complex. Software developers need to write more lines of code for the same tasks. Therefore, they argue that RISC is not the architecture of the future.

As the world enters the 21st century, the CISC Vs RISC argument has been swept aside by the recognition that neither terms are accurate in its description. The definition of ‘Reduced’ and ‘Complex’ instructions has begun to blur. RISC chips have increased in their complexity, and CISC chips have become more efficient. The figure below shows the basic partition of CISC and RISC architecture.

In the aftermath of the CISC-RISC conflict, a new enemy has appeared. EPIC (Explicitly Parallel Instruction Computing) was developed by Intel for the server market, and it will definitely appear in desktops over the next few years.

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