Memory Address Decoding in Microprocessor

Memory Address Decoding in Microprocessor – When designing an interface circuit for a microprocessor, we need to determine the number of address lines on the memory chip. Some of the microprocessor’s address lines, along with control signals, may be used to design a decode logic circuit to enable the memory chip. So the memory address decoding is a technique to connect the address lines and CS pin of the memory chip to the address lines and control lines of the microprocessor.

There are two address-decoding techniques used to connect the address lines and the CS pin of the memory chip to the microprocessor’s address and control lines.

1. Absolute/Full Memory Decoding Technique
2. Partial/Linear Memory Decoding Technique

Absolute/Full Memory Decoding Technique

In the absolute/full decoding technique, all the higher address lines are decoded to select the memory chip. The memory chip is selected only for the specified logic levels on these high-order address lines; no other logic level can select the memory chip. This addressing is normally used in a large memory system. One of the examples of this technique is shown in the figure below.

A memory map corresponding to the above figure is shown in the table below. It can be seen from the table that the address of each register in the memory chip RAM or EPROM is unique.

	A15	A14	A13	A12	A11	A10	A9	A8	A7	A6	A5	A4	A3	A2	A1	Address
Starting address of EPROM	0	0	0	1	1	1	0	0	0	0	0	0	0	0	0	1C00H
Ending address of EPROM	0	0	0	1	1	1	1	1	1	1	1	1	1	1	1	1FFFH
Starting address of RAM	0	0	1	1	1	1	0	0	0	0	0	0	0	0	0	3C00H
Ending address of RAM	0	0	1	1	1	1	1	1	1	1	1	1	1	1	1	3FFFH

Partial/Linear Decoding Technique

In small systems, the partial/linear decoding technique is used. In this technique, hardware for decoding logic can be reduced by using some of the higher-order address lines to select memory chips. The figure below shows the addressing of RAM with a partial decoding technique.

As some lines of the address bus are not connected in the hardware design, the logic at those lines is considered as don’t care. So it can take any logic, either zero or one. Depending on these states (zero or one), a single hardware design can have multiple address ranges (shadow address ranges) while taking all the don’t care lines at zero, the carrying address is taken as the primary address, and all other combinations of don’t care logic produces its foldback, mirror, or shadow address range.

In the above figure, address lines A₁₃ and A₁₄ of the address bus are not connected in the hardware design. These two address lines are don’t care lines, i.e., A₁₃ = X and A₁₄ = X. A memory map corresponding to the above figure is shown in the table below.

	A15	A14	A13	A12	A11	A10	A9	A8	A7	A6	A5	A4	A3	A2	A1	A0	Address
Starting Address Ending Address	1 1	X (0)	X (0)	0 0	1 1	1 1	0 1	0 1	0 1	0 1	0 1	0 1	0 1	0 1	0 1	0 1	8C00H 8FFFH
Starting Address Ending Address	1 1	0 0	1 1	0 0	1 1	1 1	0 1	0 1	0 1	0 1	0 1	0 1	0 1	0 1	0 1	0 1	AC00H AFFFH
Starting Address Ending Address	1 1	1 1	0 0	0 0	1 1	1 1	0 1	0 1	0 1	0 1	0 1	0 1	0 1	0 1	0 1	0 1	CC00H CFFFH
Starting Address Ending Address	1 1	1 1	1 1	0 0	1 1	1 1	0 1	0 1	0 1	0 1	0 1	0 1	0 1	0 1	0 1	0 1	EC00H EFFFH

Since A₁₃ and A₁₄ are don’t care lines, by taking A₁₄ = 0, A₁₃ = 0, then the address range is 8C00H to 8FFF (primary range), and for all other combinations 01, 10, and 11, the address ranges are AC00H to AFFFH, CC00H to CFFFH, and EC00H to EFFFH (shadow range). Whether any of these address ranges is used, the selected register of the memory will be the same.

Comparison between Absolute/Full and Partial/Linear Decoding

The difference between absolute/full and partial/linear decoding is show in table below.

S.NO.	Absolute/Full Decoding	Partial/Linear Decoding
1.	All higher address lines are decoded to select the memory or I/O device.	Few higher address lines are decoded to select the memory or I/O device.
2.	More hardware is required to design the decoding logic.	The hardware required to design decoding logic is less, and sometimes it can be eliminated.
3.	Higher cost for the decoding circuit.	Less cost decoding circuit.
4.	No multiple address.	Multiple address.
5.	Used in large systems	Used in small systems.