Programmable Communication Interface (USART) 8251 YASH PAL, April 21, 2026April 21, 2026 Programmable Communication Interface (USART) 8251 – Most of the microprocessors are designed for parallel communication. In parallel communication, the number of lines required to transfer data depends on the number of bits to be transferred. The 8085 microprocessor transfers 8 bits of data simultaneously over 8 data lines. However, in many applications, parallel communication is either impractical or impossible. In these applications, serial communication is used, whereby one bit at a time is transferred over a single line.In serial communication, an 8-bit parallel data stream should be converted into a stream of eight serial bits. After the conversion, serial bits are transmitted to the peripheral over a single line. The hardware approach to serial communication includes the programmable communication interface (USART) 8251. The USART stands for Universal Synchronous Asynchronous Receiver Transmitter. It is a programmable device, i.e., its functions and specifications for serial communication can be determined by writing instructions in its internal registers. This is a universally acceptable IC that can operate in synchronous and asynchronous modes as a receiver as well as a transmitter. The 8251 (USART) is a 40-pin IC as shown in Figure 1.Figure 1: Pin Diagram of 8251Block Diagram of 8251As shown in the block diagram in Figure 2. It is divided into five groups.R/W Control LogicTransmitter SectionReceiver SectionModem ControlData Bus BufferFigure 2: Block Diagram of 8251R/W Control LogicIt performs interfacing and determines the function of the chip according to the control word in the register. The signals associated with this block are as follows:RD (Read): It is an active low signal. It goes low for read operations, like reading status or input data from the data buffer.WR (Write): It is an active low signal. It goes low for write operations, like writing the control word or sending output to the data buffer.CLK (Clock): It is the connection to the system clock to communicate with the microprocessor.C/D (Control/data): When this signal is at logic 1, the control register or status register is addressed, and when it goes low, the data buffer is addressed.CS (Chip Select): It is an active low signal. When it goes low, the 8251 chip is selected.RESET: It is an active high signal. When it goes high, reset the 8251.Transmitter SectionIt consists of a buffer register to hold eight bits and an output register to convert all eight bits to serial bits. It consists of the following signal.TXD (Transmitter Data Output): It is an active high output pin. It is used to transmit serial data bits along with other information like start bit, stop bit, and parity bit.TXC (Transmitter Clock Input): It is an active low output pin. It controls the rate at which the character is to be transmitted.TXRDY (Transmitter Ready): It is an active high-output pin. It is used to inform the microprocessor that the transmitter is ready to accept new data for transmission from the microprocessor.TXE (Transmitter Empty): It is an active high-output signal. It goes high when 8251 has no data to transmit.Receiver SectionIt consist following signals:RXD (Receiver Data Input): It is an active low input pin. It is used to receive serial data.RXC (Receiver Clock Input): It is an active low input pin. It controls the rate at which the character is to be received.RXRDY (Receiver Data Read): It is an active high-output pin. It is used to indicate that the 8251 contains data to be read by the microprocessor. This pin can be used to check the status or to interrupt the microprocessor.SYNDET/BD (Synchronous Detect/Break Detect): In synchronous mode, it is used for detecting synchronous characters. In this mode, it may be used as input or output. When used as an input, a signal at this pin causes 8251 to start assembling a data character. When used as an output, the SYNDET pin goes high to indicate that the 8251 has located a synchronous character. In asynchronous mode, the pin acts as a break detect output. It goes high whenever the RXD pin goes low, through two consecutive stop bit sequences.Modem ControlIt is used to establish data communication. It converts digital data into audio tone frequencies for transmission over telephone lines and converts audio frequencies into digital data for reception.Data Bus BufferIt is a bidirectional register, which is used as an input/output port to accept/send data. With the C/D signal low.Initialization of 8251It is necessary that the microprocessor inform the 8251 about mode, band, stop bit, parity, etc. When the data is transferred, through a set of control words. The 16-bit control word is divided into two parts, the mode word and the command word. The microprocessor must also check the status word by reading the status register for the readiness of the peripheral. The mode word is shown in Figure 3, the command word in Figure 4, and the status words are shown in Figure 5.Figure 3: Mode register of 8251Figure 4: Command word of 8251Note: Error reset must be performed whenever RX enable and enter hunt are programmed.ModeCommand WordEHEnable hunt mode1 = Enable search for sync charactersIRInternal reset1 = Resets 8251 to modeRTSRequest to send1 = Enable RSTERError Reset1 = Reset error flags PE.OE.FESBRKSend break character1 = Forces TxD “Low”0 = Normal operationR x EReceive enable1 = Enable0 = DisableDTRData terminal enable1 = Enable DTRT x ENTransmit enable1 = Enable0 = DisableCommand word modes of 8251Figure 5: Status word of 8251ModeStatus registerDSRData set ready:Indicates that the DSR is at a zero level.SYNDET/BRKDETSame definitions as I/O pins.FEFraming Error (Asynch only)The FE flag is set when a valid stop bit is not detected at the end of every character. It is reset by the ER bit of the command instruction. FE does not inhibit the operation of the 8251A.OEOverrun ErrorThe OE flag is set when the CPU does not read a character before the next one becomes available. It is reset by the ER bit of the command instruction. OE does not inhibit the operation of the 8251A. However, the previously overrun character is lost.PEParity ErrorThe PE flag is set when a parity error is detected. It is reset by the ER bit of the command instruction. PE does not inhibit the operation of the 8251A.T x EMPTYSame definitions as I/O pins.R x RDYSame definitions as I/O pins.T x RDYNote 1Status register modes of 8251Transmission Formats of 8251The data transmission/reception in the serial communication may be performed in two formats:Asynchronous transmission/receptionSynchronous transmission/receptionThese communication modes can be enabled by writing proper mode and command instructions. The mode instruction defines the baud rate (in case of asynchronous mode), character length, number of stop bits, and parity type. After writing the mode instruction, the appropriate command instruction is written.Asynchronous Transmission/ReceptionFigure 6 shows the format for asynchronous transmission. Asynchronous formats are character-oriented. In this, the bits of a character or data word are sent at a constant rate, but characters can come at any rate (asynchronous) as long as they do not overlap. When no characters are being sent, a line stays high at logic 1. This signal is called mark, whereas logic 0 is called space. The start of a character is indicated by a start bit, which is always low. The start bit is used to synchronize the transmitter and receiver. After the start bit, the data bits are sent and followed by one or more stop bits. The stop bits show the end of a character. Different systems use 1, 1 ½, or 2 stop bits. The combination of start bit, character, and stop bit is known as a frame.Figure 6: Asynchronous transmission of 8251The data rate can be expressed as bits/sec. This is also known as the baud rate.Note: The start and stop bits carry no information, but are required because of the asynchronous nature of data.Synchronous Transmission/ReceptionThe start and stop bits in each frame cause the overhead bytes in actual information, which reduces the overall character rate. This problem can be eliminated by synchronizing the receiver and transmitter. These two can be synchronized by using the same clock signal. Figure 7 shows the synchronous transmission.Figure 7: Synchronous Transmission of 8251Software approach for Serial Communication – As discussed in the 8085 Microprocessor Architecture, the 8085 microprocessor communicates serially using two lines: SOD and SID. The SOD line is used to send data serially, and the SID line is used to receive data serially through SIM and RIM instructions. These two instructions are discussed with interrupts. The SIM instruction places the D7 bit of the accumulator at the line SOD if the D6 bit (SDE) of the accumulator is high. It means the SDE (serial data enable) bit, when set, enables serial communication, and the 8085 microprocessor sends the status of the SOD bit on the SOD pin. The RIM instruction is used to receive one bit of data on the SID pin of the 8085 microprocessor. After execution of the RIM instruction, the data on the SID line will be copied to the D7 bit of the accumulator. engineering subjects Microprocessor microprocessor