8085 Microprocessor Timing Operations

8085 Microprocessor Timing Operations – The program is a set of instructions written in a sequence and performs predefined tasks whenever executed. The 8085 microprocessor is designed to execute 74 different instruction types. To execute an instruction, the microprocessor needs to perform various operations related to memory and/or input/output devices. These predefined operations are known as Timing Operations and are further divided into T-states.

Before understanding the timing operations of the 8085 microprocessor, we need to understand what is Instruction cycle and a machine cycle.

Instruction Cycle – The instruction cycle is defined as the time required to complete the execution of an instruction. The 8085 microprocessor instruction cycle may include one to six operations to complete the execution of one instruction.

Machine Cycle – Machine Cycle is defined as the time required to complete one operation. The operation can be accessing memory, input/output, or acknowledging an external request. In other words, to move a data byte in or out of the microprocessor, a machine cycle is required. One instruction cycle consists of 1 to 4 machine cycles.

There are nine different types of machine cycles in the 8085 microprocessor. The status signals S₁, S_0, and IO/M are generated at the start of any machine cycle and remain valid for the whole duration of the machine cycle. All the operation and their associated status signals are listed in the table below.

Here, Z = Tri-state and X = Don’t care

8085 Microprocessor Timing Operations

An instruction cycle is defined using the time required to perform one instruction operation, and an instruction cycle can use multiple machine cycles to operate. A machine cycle has 1 to 6 Timing States that it uses to operate. So these timing states are further known as timing operations in a microprocessor.

Timing (T-state) operation

T-state is defined as one subdivision of the operation performed in one clock period. This is the unit in which the time of any operation is measured. These subdivisions are internal states, synchronized with the system clock. The terms T-state and clock period are often used synonymously. Each machine cycle consists of 3 to 6 T-states.

How to Recognize Machine Cycles and T-states in an Instruction Cycle

The instruction cycle is the time required to completely read and execute the instruction. Hence, the instruction cycle can be divided into two parts:

1. The time during which instruction (opcode and operand) is read.
2. The time at which the operation is performed.

The first operation of the instruction cycle is always reading the opcode. This is known as the opcode fetch machine cycle. After that, read the byte written in the instruction. This is a memory read machine cycle. For example, if instruction MVI A, 70H is executed, there will be an opcode fetch machine cycle (to read the opcode) first, and then a memory read machine cycle (to read the data 70H).

The fundamental rule to find the machine cycles in an instruction cycle is to first find the number of memory bytes required to store the instruction. The number of memory bytes is equal to the number of machine cycles. Out of these machine cycles, the first will be opcode fetch, and the remaining will be memory read always. For a single-byte instruction, that byte is opcode only, so only an opcode fetch machine cycle will be needed.

When the instruction is completely read and decoded, its operation begins. But for operation instruction, additional machine cycles are only required when the operation requires any communication with memory or input/output. Operations related to internal data operations do not require any extra cycles. For example, if an instruction instructs the microprocessor to store 1-byte data in memory, then one execution cycle (memory write) will be additional. Therefore,

Instruction Cycle = Opcode fetch and/or read cycles + execution cycles

The length of opcode fetch machine cycles is not fixed. It varies from 4T states to 6T states as per the instruction. In most cases, it is 4T-states. Other memory and input/output-related operations have a length of 3T-states. Hence, after finding the machine cycles, as the corresponding T-states are already known, one can easily calculate the number of T-states just by summing the T-states of the individual machine cycle.

Example Question: The 8085 microprocessor is operating at a 2 MHz clock signal. Calculate the time required to execute the following instructions:

1. MVI A, 30H
2. MOV A, B
3. STA 3050H

Solution

(i) MVI A, 30H

Number of bytes required to store the instruction = 2 bytes. Hence, the first part of the instruction cycle requires two machine cycles. Out of these, the first will be opcode fetch, and the remaining one will be memory read. Now the meaning of this instruction MVI A, 30H is to copy the contents 30H to the accumulator. This is an internal operation, and there is no operation related to memory or input/output. Therefore, no additional machine cycles are needed. Hence,

Instruction Cycle = Opcode fetch + Memory read (One).
Total T-states = 4T + 3T = 7T
The microprocessor frequency (F) = 2MHz
                                 = 2 x 106Hz
Total time required to execute instruction = 7T
= 7(1/F)
= 7/(2x106) sec
= 3.5 μsec

(ii) MOV A, B

Number of bytes required to store the instruction = 1 byte. Hence, the first part of the instruction cycle requires only one machine cycle, i.e., opcode fetch. Now the meaning of this instruction MOV A, B is to copy the contents of register B to the accumulator. This is an internal operation and does not need any additional machine cycles. Hence

Instruction cycle = Opcode fetch
Total T-states = 4T
The microprocessor frequency (F) = 2MHz
= 2 x 106Hz
Total time required to execute instruction = 4T
= 4(1/F)
= 4/(2x106) sec
= 2μ sec

(iii) STA 3050H

Number of bytes required to store the instruction = 3 bytes. Hence, the first part of the instruction cycle requires three machine cycles. Out of these, the first will be opcode fetch, and the remaining two are memory read. The meaning of the instruction, STA 3050H, is to store the contents of the accumulator into the memory location 3050H. This operation requires one additional machine cycle, i.e., memory write. Hence

Instruction cycle = Opcode fetch + Memory read (two) + Memory write (one)
Total T-states = 4T + 3T + 3T + 3T
= 13T
The microprocessor frequency (F) = 2MHz
= 2 x 106Hz
Total time required to execute instruction = 13T
= 13(1/F)
= 13/(2x106) sec
= 6.5 μ sec