Timing Diagram of 8085 Microprocessor

Timing Diagram of 8085 Microprocessor – A timing diagram is the pictorial representation of the execution of an instruction with a time axis. The timing diagram shows when the signals are activated and for what period they remain in an active state.

Timing Diagrams of 8085 Microprocessor Signals

The 8085 microprocessor has a number of signals that are generated or activated at a specific instant for a specific time period. These signals are represented in a timing diagram in a different manner.

Single signal – This is represented by a line. It can have a status of either logic ‘0’ or logic ‘1’ or tri-state. The change in the state of the signal takes finite time. Hence, the state change of the signal is represented with finite rise time and fall time. This is shown in below figure.

Group of Signals (Bus) – This is represented in the form of a block. Data bus and address bus are represented by a group of signals. This is shown in the figure below.

Clock signal – The operating frequency of the 8085 microprocessor is half of the frequency provided at X₁ and X₂ pins. All the operations are synchronized with the operating frequency. In the timing diagram, the operating frequency clock signals are always on the top, and then other signals are shown with reference to the clock. This is shown in the figure below.

Address Latch Enable (ALE) – This is activated at the beginning of the T₁ state of each machine cycle and goes low just at the end of the T₁ state. This is an active high signal and is used to demultiplex the address data bus. This is shown in the figure below.

High-order Address Bus (A₈ – A₁₅) – The high-order address bus is available during the T₁, T₂, and T₃ states of each machine cycle. This is shown in the figure below.

Low Order Address Bus (A₀ – A₇) – The low order address bus is available during the T₁ state of each machine cycle. This is represented in the figure below.

Data Bus (D₀ – D₇) – The data is transferred between the processor, input/output devices, and memory through the data bus during T₂ and T₃ states. In the read cycle, data will appear on the data bus during the later part of T₂, and in the write cycle, data will appear on the data bus at the beginning of the T2 state. This is shown in the figure below.

Status Signals – There are three status signals in the 8085 microprocessor. They are activated at the beginning of the T₁ state and remain active till the end of the machine cycle. Status signals are important to finalize the type of machine cycle. This is shown in the figure below.

RD and WR signals – The direction of data transfer is decided by RD and WR signals. For the reading operation, the RD signal goes low at the beginning of T₂ and T₃, whereas for the writing operation, the WR signal goes low at the end of T₂ and T₃. These are active-low signals and are shown in the figure below.

Timing Diagrams of 8085 Machine Cycles

Time required to complete one operation of accessing memory, input/output, or acknowledgement is defined as a machine cycle. There are various types of machine cycles. Timing diagrams for them are discussed below.

Opcode Fetch Machine Cycle – The first machine cycle of each instruction is an opcode fetch cycle. In the opcode fetch machine cycle, the microprocessor reads and interprets the nature of the instruction to be executed. This machine cycle takes 4T states or 6T states, as shown in the figure below, to complete one operation.

1. State T₁ – In T₁ state, the microprocessor places the high-order address (PC_H) on the high-order address lines (A₈ – A₁₅) and the low-order address (PC_L) on the low-order multiplexed address/data line (AD₀ – AD₇). The ALE signal is activated by the microprocessor to latch the low-order byte of the address in the external latch. ALE signal goes low again at the end of T₁ state. The status signals are: IO/M = 0, S₁ = 1 and S₀ = 1.
2. State T₂ – In this state, the low-order address disappears from AD₀ – AD₇, and these lines are used as a data bus. The high-order address bus and status signals remain unchanged in the T₂ state. RD signal goes low, and after that, the opcode of the instruction is loaded to the data bus.
3. State T₃ – During T₃, the 8085 microprocessor loads the data from the data bus into its instruction register and raises RD to high, which disables the memory.
4. State T₄ – In the T₄ state, the 8085 microprocessor decodes the meaning of instruction. The meaning of instruction decides whether to enter in T₅ and T₆ states of machine cycle or not.
5. State T₅ and state T₆ – In states T₅ and T₆, the microprocessor completes the internal operation if required by the instruction.

Memory Read Machine Cycle – The memory read machine cycle is performed when a data byte other than the opcode is to be read from the memory. The timing diagram of the memory read machine cycle is shown in the figure below.

The memory read machine cycle is similar to the opcode fetch machine cycles. In both machine cycles, the microprocessor reads the memory. In opcode fetch, memory contents are treated as an opcode, whereas in memory read, memory contents are treated as simple data. There are only two differences in the opcode fetch and memory read timing diagram.

1. The memory read cycles use only T₁ to T₃ states. T₄ state is not used because there is no need to find the meaning of data, read from memory.
2. The status signals S₁S₀ = 10 rather than 11. These status signals are used by the microprocessor to differentiate the machine cycles.

Memory Write Machine Cycle – Memory write machine cycle is performed when data is to be written into the memory. The timing diagram of the memory write machine cycle is shown in the figure below.

The memory write machine cycle is also of 3T-states, similar to the memory read machine cycle. The memory write cycle uses only T₁ to T₃ states. The difference between these two machine cycles is that the WR control signal is used in the memory write cycle instead of the RD signal used in the memory read cycle. It is important to note that in the T₂ state of the memory write cycle, the microprocessor places data on the data bus and then sends the WR signal to write the data from the data bus to the specified memory location. Another difference between the memory read and memory write cycles is the status signals (S₁, S₀, and IO/M). The status signals for the memory write machine cycle are: IO/M = 0, S₁ = and S₀ = 1.

Input/Output Read Machine Cycle – This cycle is used by the microprocessor to read the information present on an input port through the data bus. As the address of the port is 8-bit (peripheral-mapped I/O), the lower and higher order address buses have the same port address. It means the microprocessor copies the 8-bit address to the low-order address bus (A₀ – A₇) as well as to the high-order address bus (A₈ – A₁₅). The timing diagram for the input/output read machine cycle is shown in the figure below.

The input/output read machine cycle also uses three T-states (T₁ to T₃ states) and is similar to the memory read machine cycle, with two differences.

1. Since the port address is 8 bits, it will be copied to both the high-order and low-order address bus.
2. The status signal IO/M = 1, instead of 0. This is because the operation is related to an input/output device rather than memory.

Input/Output Write Machine Cycle – The input/output write machine cycle is used by the microprocessor to send the information on the output port. The timing diagram of the input/output write machine cycle is shown in the figure below.

The input/output write machine cycle also uses three T-states (T₁ to T₃ states). This machine cycle is similar to the memory write machine cycle, with the two differences:

1. Since the port address is 8 bits, it will be copied to both the high order (A₈ – A₁₅) and low order (A₀ – A₇) address bus.
2. The operation is related to the input/output device instead of memory; the status signal IO/M = 1 rather than 0.

Other machine cycles are not discussed here to maintain the simplicity of the text.