Stack in 8085 Microprocessor

Stack in 8085 Microprocessor – The stack is a portion of R/W memory that is used for temporary storage during the execution of a program. For the application programs, the internal memory of the microprocessor (registers) is not sufficient to store the intermediate results. These intermediate results can be stored temporarily on the stack and can be used again when required. The data is put last will be taken first. This type of input/output manner is called Last In First Out (LIFO).

Microprocessor Stack

The 8085 Microprocessor stack follows the LIFO concept. When the data is written on the stack, the operation is called PUSH. Similarly, when the data is read from the stack, the operation is called POP. The stack is generally initialized at the highest available memory location. The beginning of the stack is defined by loading the address into the stack pointer (SP). The stack pointer is a 16-bit register that indicates the top of the stack. Top of the stack means the data that is recently stored can be retrieved first. A new register pair, Program Status Word (PSW)) is also used with stack-related operations. The program status word is a 16-bit register pair. It is the combination of the accumulator and the flag register.

Stack Related Instructions

Execution of PUSH R_p/PSW – In the PUSH operation, 16-bit data from register pair R_p/PSW is stored on the stack. This is completed with two internal operations. In the first operation, the stack pointer is decremented by one, and the higher data byte (D₈ – D₁₅) of the 16-bit data is stored at the memory location pointed by the stack pointer. In the second operation, the stack pointer is again decremented by one, and the lower data byte (D₀ – D₇) of the 16-bit data is stored at the memory location pointed by the stack pointer. Figure 2 shows the steps involved in the PUSH operation.

The instruction cycle of any instruction has two parts: the Read cycle and the execution cycle. The read cycle of the PUSH R_p instruction has only one machine cycle, i.e., opcode fetch. The execution cycle of this instruction requires two additional machine cycles to write the two bytes to memory. Hence, execution has two memory write machine cycles.

Instruction = Read cycle + Execution cycle
= (Opcode fetch) + (Memory Write + Memory Write)

Total T-states required
= 6T + (3T + 3T)
= 12T

The timing diagram of the instruction PUSH R_p is shown in Figure 3.

Note: The opcode fetch machine cycle of instruction PUSH Rp/PSW requires 6 T-states instead of 4 T-states.

Execution of POP R_p/PSW – In the POP operation, 16-bit data is retrieved from the stack to the register pair R_p/PSW. This stack also includes two internal operations. In the first operation, the lower data byte (D₀-D₇) is retrieved from the stack memory location pointed by the stack pointer and loaded into the lower byte of the register pair. Then the stack pointer is incremented. In the second operation, a higher data byte (D₈ – D₁₅) is retrieved from the stack memory location pointed by the stack pointer and loaded to the higher byte of the register pair. Then the stack pointer is incremented as shown in Figure 4, which shows the steps involved in POP operations.

Similar to other instructions, the POP R_p instruction also has two parts: the Read cycle and the Execution cycle. The read cycle of instruction POP Rp has only one machine cycle, i.e., opcode fetch. The execution cycles of this instruction require two additional cycles to read (retrieve) the two bytes from memory. Hence, the execution cycle has two memory read machine cycles.

Instruction = Read cycle + Execution cycle
= (Opcode fetch) + (Memory Read + Memory Read)
Total T-states required
= 4T + (3T + 3T)
= 10T

The timing diagram of the instruction POP R_p is shown in Figure 5.