8255 (PPI) Programmable Peripheral Interface

8255 Programmable Peripheral Interface – The 8255 (PPI) is a programmable, parallel input/output device. It can be programmed to transfer data under different conditions, from simple input/output. It is flexible, versatile, and economical (when multiple input/output ports are required), but somewhat complex. It is widely used with almost any microprocessor.

8255 (PPI) Programmable Peripheral Interface

The 8255 Programmable Peripheral Interface has 40 pins; out of these, 24 input/output pins can be grouped in 8-bit parallel ports: Port A and Port B, with the remaining eight bits as Port C. Port C can be used as an individual or be grouped in two 4-bit ports, namely, port C_UPPOER (C_U) and port C_LOWER (C_L) as shown in Figure 1. The function of these ports is defined by writing a control word in the control register.

Block and Pin Diagram of the 8255 Interface

The block diagram is shown in Figure 2 and the pin diagram in Figure 3, with various elements and their functions as follows:

Parallel Ports

1. Port A: Contains 8 pins (PA₀ – PA₇) for receiving/sending data, it is used as an 8-bit parallel port.
2. Port B: Also used as an 8-bit parallel port. It contains 8 pins (PB₀ – PB₇) for receiving/sending data.
3. Port C: Used as an 8-bit parallel port. It can be divided into two 4-bit ports: CUPPER (CU) and CLOWER (CL). It contains 8 pins (PC₀ – PC₇) for receiving/sending data. Port C pins can also be used for handshake signals.

Control Logic

The control section has six lines. Their functions are as follows:

1. RD (Read): This control signal enables the read operation. This is an active low signal. When it goes low, the microprocessor reads data from a selected input/output port of the 8255.
2. WR (Write): This control signal enables the write operation. This is also an active low signal. When it goes low, the microprocessor writes into a selected input/output port or the control register.
3. RESET (Reset): It clears the control register and sets all ports in the input mode. It is an active high signal.

Address Logic

1. A₀, A₁: These pins are generally connected to microprocessor address lines – A₀ and A₁. The combination of these two is used to identify the address of various ports and the control register. For this purpose, an internal decoder is used.

2. CS (Chip Select): It is the master chip select signal. It is an active low signal. When it goes low, the chip will be selected. Address lines other than A₀ and A₁ may be used in any combination to make the chip select logic. Addresses of ports and control registers can be determined by a combination of CS, A₁, and A₀ lines. This is shown in the table below and in Figure 4.

Control Register

The register, which is internal to the 8255 chip, is called the control register. The contents of this register are known as the control word. The control word specifies the input/output function and modes of various ports of the 8255. The control register can be accessed to write a control word when both A₀ and A₁ are high, as shown in the table for Address decoding of 8255.

Interfacing Steps of Microprocessor with 8255

To communicate with peripherals through the 8255, three steps are necessary.

1. Determine the address of ports A, B, and C and of the control register by the use of the chip select logic and address lines A₀ and A₁.
2. Determine the control word and write it into the control register.
3. Write input/output instructions to communicate with the peripheral through ports A, B, and C.

Note: The control register can’t be used for the reading operation.

Modes of 8255

All the functions of 8255 are classified according to two modes.

1. BSR (bit set/reset) Mode
2. Input/Output Mode

The modes of 8255 are shown in Figure 5.

BSR (Bit Set/Reset) Mode

The BSR mode includes only eight bits of port C, which can be set or reset by writing the suitable control word in the control register. In BSR mode, the D₇ bit of the control word is at logic 0, and it does not affect the previously transmitted control word with bit D₇ = 1; this indicates that input/output operations of ports A and B are not altered by a BSR control word.

BSR Control Word: BSR control word sets or resets one bit at a time of port C. When written in the control register. The control word format for this mode is shown in Figure 6.

Input/Output Mode in 8255

Input/output mode is used to transfer the data to or from the peripherals. The D₇ bit of the control word must be set (1) for this mode. Three different types of input/output modes are available in the 8255.

1. Mode 0 – Simple input/output mode
2. Mode 1 – Input/output with handshake signals
3. Mode 2 – Bidirectional mode

Control word format – The control word format is shown in Figure 7.

Mode 0 – Simple input/output mode

In this mode, Ports A and B are used as two simple 8-bit Input/Output ports and Port C as two 4-bit ports. Each port (or half-port in the case of port C) can be programmed to function as simply an input port or an output port.

Mode 1 – Input/output mode with handshake

In this mode, input or output data transfer is controlled by handshake signals. Handshake signals are used to transfer data between devices whose data transfer speeds are not the same. The handshaking signals are used to inform the microprocessor whether the peripheral is ready to communicate or not. In mode 1, handshake signals are exchanged between the microprocessor and peripherals prior to the data transfer. The features of this mode include the following:

1. Port A and Port B function as 8-bit input/output ports.
2. Each port uses three lines from port C as handshake signals. The remaining two lines of port C can be used for simple input/output functions.

In the 8255, the specific lines from port C are used for handshake signals. These lines are very similar to the input/output function of a port. Therefore, input and output functions in mode 1 are discussed separately.

Mode 1: Input Control Signals

When both port A and port B are configured as input ports, and port C is used for handshake signals. Port A uses the upper three lines of port C, PC₃, PC₄, and PC₅, whereas port B uses the lower three lines: PC₀, PC₁, and PC₂. The functions of these signals are as follows:

1. STB (Strobe input): This is an active low input signal generated by a peripheral device to indicate that it has transmitted a byte of data. In response to STB, the 8255 generates IBF and INTR signals as shown in the figure below.
2. IBF (Input Buffer Full): This is an active high output signal. This signal is an acknowledgement by the 8255 to indicate that the input latch has received the data byte. This is reset when the microprocessor has read the data.
3. INTR (Interrupt Request): This is an active high output signal that may be used to interrupt the microprocessor. This signal is generated if STB, IBF, and INTE (Internal Flip-flop) are all at logic 1. This is reset by the falling edge of the RD signal.
4. INTE (Interrupt Enable): This is an internal flip-flop used to enable or disable the generation of the INTR signal.

The two flip-flops INTE_A and INTE_B are set/reset using the BSR mode. The INTE_A is enabled or disabled through PC4, and INTE_B is enabled or disabled through PC₂. The timing waveform for the strobed input (with handshake) is shown in Figure 9.

Control Word – To configure port A and port B as input ports in mode 1, the control word, according to the format shown in Figure 9 “8255 Control Word format for input/output mode“, will be as follows:

Status Word – When we read port C in mode 1, the bit pattern loaded into the Accumulator is called the status word. The status word for mode 1, when both port A and port B are configured as input ports, is as follows:

Mode 1: Output Control Signals

When both port A and port B are configured as output ports, port C is used for handshake signals. The functions of various output control signals are as follows:

1. OBF (Output Buffer Full): This is an output signal that goes low when the microprocessor writes data into the output latch of 8255. This signal indicates to an output peripheral that new data are ready to be read; it goes high again after the 8255 receives an ACK signal from the peripheral.
2. ACK (Acknowledge): This is an active low input signal. It is generated by the peripheral after receiving data from the output latch of 8255. When it goes low, OBF goes high again, indicating that the output buffer is empty.
3. INTR (Interrupt Request): This is an active high output signal, which may be used to interrupt the microprocessor by connecting it to any of the interrupt pins. The INTR is set when OBF, ACK, and INTE are all at logic 1. This is reset by the falling edge of the WR.
4. INTE (Interrupt Enable): This is an internal flip-flop, which is used to enable or disable the generation of the INTR signal. The two flip-flops INTE_A and INTE_B are controlled by bits PC₆ and PC₂, respectively, through the BSR mode.

Control Word – To configure port A and port B as output ports in mode 1, the control word, according to the format shown in the above figure “8255 Control Word format for input/output mode” will be as follows:

Status Word – When we read port C in mode 1, the bit pattern loaded into the accumulator is called the status word. The status word for mode 1, when both port A and port B are configured as output ports, is as follows:

The timing waveform for the strobed output (with handshake) is shown in Figure 11.

Mode 2: Bidirectional Data Transfer

This mode allows bidirectional data transfer (transmission and reception) over a single 8-bit data bus only in group A, with port A as the 8-bit bidirectional data bus; and lines PC₃ – PC₇ are used for handshaking purposes. Port B can be configured in mode 0 or in mode 1. If port B is configured in mode 0, the three pins (PC₀, PC₁, and PC₂) may be used for input/output purposes as shown in Figure 12.

Whereas if port B is configured in mode 1, then these three pins (PC₀, PC₁, and PC₂) will also be utilized by handshake signals for port B, as shown in Figure 13.

Programming the 8255 in Mode 1

The 8255 can be programmed using the following two techniques:

1. Status check Input/Output
2. Interrupt Input/Output

Status check Input/Output

In this technique, the microprocessor reads the status word from port C, checks for a particular status bit in a loop until it gets the proper status to synchronise with the slow peripheral. This is the use of handshake signals, where, before transmitting data, the status of the slower peripheral is checked. Whether it is ready or not, otherwise the data may be lost. The status check process can be explained using the following flow chart, given in Figure 14.

Interrupt Input/Output

Interrupt Input/Output assumes that vectored interrupts are available. The INTE flip-flop is set, which will generate the INTR signal. The INTR signal is connected to any of the interrupt pins (TRAP, RST 7.5, RST 6.5, RST 5.5, or INTR) of the microprocessor. A flow chart for this type of programming can be given as shown in Figure 15.