8085 Microprocessor Memory Interfacing

YASH PAL,

8085 Microprocessor Memory Interfacing – One of the most important parts of the design of a microprocessor-based system is the design of the interface. The first part of the microprocessor interface is interfacing with the memory.

Memory Interfacing with 8085 Microprocessor

Here is the following steps need to be followed for interfacing the memory with the 8085 microprocessor.

  1. Calculate the number of address lines required.
  2. Select the address lines from the available memory space.
  3. Identify the pins that are required for the interface.
  4. Design the logic circuit to fulfill the interfacing circuit requirement to select the memory chip.

To control the reading and writing operations with memory, appropriate control signals are needed. A truth table for memory is shown in the table below.

RDWRCSCharacteristics
110No-operation
010Read data
100Write data
000Illegal
xx1Tri-state
Truth table for memory operations

Note: When CS = 1, the memory chip remains in tri-state and can not be used. If CS = 0 and RD = 0, WR = 0, then this is an illegal operation because both reading and writing operations can not be performed simultaneously.

Let’s take an example problem to understand the Memory Interfacing with the 8085 microprocessor.

We need to interface a 4K x 8-bit memory to the 8085 microprocessor. Also, we need to find the address of the last register if the first register address is F000H.

Solution: The interfacing circuit can be designed as follows:

  1. Given memory size is 4K x 8 bits. Hence, the number of address lines
= log2 (4K)
= log2 (22 x 210)
= log2 (212)
= 12

There are 12 address lines on the memory chip to identify all the registers.

  1. In the 8085 microprocessor, there are 16 address lines (A0 – A15). Out of 16 address lines, 12 address lines (A0 – A11) are connected to the memory chip.
  2. The pins available on the memory chip for interface are RD, WR, CS, and (A0 – A11). Whereas the pins available as the microprocessor for interface are IO/M, RD, WR, CS, and (A0 – A15).
  3. Leaving (A0 – A11) for direct connection from microprocessor to memory chip (12 lines), the remaining address lines (A12 – A15) and IO/M are used for the decoding circuit to generate the CS signal. To select the memory chip, CS must be equal to 0. IO/M will be 0, since the operation is related to memory. Let us design the logic circuit as shown in the Figure 1.
Decoding logic circuit
Figure 1: Decoding logic circuit

The complete interfacing circuit of a 4K x 8-bit memory to the 8085 microprocessor is shown in Figure 2.

Interfacing 4K x 8 bit memory to 8085 microprocessor
Figure 2: Interfacing a 4K x 8-bit memory to the 8085 microprocessor

The last register of the memory chip will be identified if all the address lines of memory (A0 – A11) are at high logic (1). From the decoding logic, it is clear that CS will be low only if (A12 – A15) lines are at high logic (1) with IO/M = 0.

Therefore, the address of the last register will be FFFFH.

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