Direct Memory Access (DMA) Controller 8257 – Microprocessor

Direct Memory Access Controller 8257 – Direct Memory Access (DMA) is an input/output technique commonly used for high-speed data transfer. For example, data transfer between system memory and input/output devices. In status check, input/output, and interrupt input/output, data transfer is relatively slow because each instruction needs to be fetched and executed. In DMA, the microprocessor releases the control of the buses to a device called a DMA controller. The controller manages data transfer between memory and a peripheral. It bypasses the microprocessor. It introduces two new signals available on the 8085 – HOLD and HLDA.

HOLD – This input signal requests a DMA transfer from the microprocessor. In response to this request, the microprocessor releases the buses. All buses are tri-stated, and the hold acknowledgement signal is sent out. The microprocessor regains control of buses after the HOLD request goes low.

HLDA – This active high signal is generated by the microprocessor when the microprocessor accepts the DMA request. This signal is given to the requesting DMA I/O device. This indicates that the microprocessor is releasing the control of buses.

The basic operation and interfacing of a typical DMA controller with a system are shown in the figure below.

The microprocessor communicates with the DMA controller by using the chip-select lines, buses, and control signals. This is named the slave mode of the DMA controller. However, once the DMA controller gains control, it plays the role of a processor for data transfer. This is the master mode of DMA controllers. The 8257 is a 40-pin IC. The pin diagram of 8257 is shown in the figure below.

Block Diagram of 8257 DMA Controller

8257 has four independent channels, CH0 to CH3. Internally, two 16-bit registers are associated with each channel. The figure below shows the internal architecture of the 8257 DMA controller. It includes five blocks:

Data Bus Buffer

It is a tri-state, bidirectional 8-bit buffer. This block is responsible for data transfer between the internal bus of 8257 and the microprocessor.

READ/WRITE Control Logic

It accepts address bits and control signals from the microprocessor. This is also responsible for generating address bits and control signals. The following signals are associated with this block.

1. A₀ – A₃: To access a 16-bit register, A₀ – A₃ address lines are used to distinguish between the 16-bit registers.
2. IOR (Input/Output Read Signal): It is an active-low signal, bidirectional in nature. It works as an input signal in slave mode to read the content of the internal register of the 8257. It works as an output signal in master mode to read data from a peripheral during a memory write cycle.
3. IOW (Input/Output Write Signal): It is active low signal bidirectional in nature. It works as an input signal in slave mode to write data into the internal register of 8257. It works as an output signal in master mode to load data to a peripheral during a memory read cycle.
4. CLK (Clock): It is the input clock frequency to generate timing for the internal operation of 8257.
5. RESET: It is an active high input signal. It is used to clear all the registers and to disable all the DMA channels.

Control Logic of DMA

The control logic controls the sequence of DMA operations during the DMA cycles. It also contains the mode set register and the status register. The following signals are associated with this block:

1. READY: It is an active high input signal. It is generated to indicate that the 8257 is ready for the DMA operation.
2. HRQ (Hold request): It is an active high-output signal. It is used to request the microprocessor to release the control of the system buses. After receiving the HRQ, the microprocessor releases the control of buses and generates the HLDA signal.
3. HLDA (Hold Acknowledge): It is an active high input signal. After receiving the HRQ signal from the DMA controller, the microprocessor generates the HLDA signal.
4. MEMR (Memory Read): It is an active low output signal. It is used during the DMA cycle to read from memory.
5. MEMW (Memory Write): It is also an active low output signal. It is used during the DMA cycle to write into memory.
6. AEN (Address Enable): It is an active high output signal. It is used to latch a high-order address byte to generate a 16-bit address.
7. AD STB (Address Strobe): It is an active high-output signal. It also goes high when AEN goes high.
8. TC (Terminal Count): It is an active high-output signal. It goes high when the data transfer process is over, and the count register reaches zero.
9. MARK: It is an active high-output signal. It goes high after transferring every 128 bytes of data block.

Priority Resolver

Priority resolver is used to resolve the priority of the channels. It can be initialized either in rotating or fixed priority mode.

DMA Channel

8257 has four separate channels, and each channel contains two 16-bit registers: an address register and a terminal count register. The address register is used to hold the starting address of memory. After each DMA cycle, the register is incremented. F/L flip-flop is used to distinguish between lower and higher bytes of the 16-bit between lower and higher bytes of the 16-bit address register. To access the lower byte of a 16-bit register, the F/L flip-flop should be reset, and for the higher byte of a 16-bit register, the F/L flip-flop should be set. The format of the address register is shown in the figure below.

The following signals are associated with channel 0 to channel 3.

1. DRQ₀ – DRQ₃ (DNA Request): These are active high input signals for channel 0 to channel 3, respectively. These signals are generated from the peripheral to the respective channel whenever the peripheral is ready for data transfer.
2. DACK₀ – DACK₃ (DMA Acknowledge): These are active low output signals generated from channel 0 to channel 3. These signals are used to inform the individual peripherals that a DMA is granted.

Mode Set Register and Status Register

Two additional registers, called the mode set register and the status register, are shown in the two figures below.

Operating Modes of DMA Controller

The 8257 operates in the following modes:

Rotating Priority Mode

8257 operates in rotating priority mode when the D₄ bit of the mode set register is high. After each DMA cycle, the priority of each channel changes. Initially, CH – 0 has the highest priority, and CH – 3 has the lowest priority. The channel that has just been serviced will get the lowest priority, after the DMA cycle, and other channels move up to the next higher priority levels. The rotating pattern of channels is shown in the figure below.

Fixed Priority Mode

8257 operates in fixed priority mode when the D₄ bit of the mode set register is low. CH – 0 has the highest priority, and CH – 3 has the lowest priority. The priority of each channel remains unchanged during the complete operation.

Extended Write Mode

8257 operates in extended priority mode when the D₅ bit of the mode set register is high. This mode is used to interface the peripheral with different access times. If the peripheral is slower, then for synchronization, the READY signal is used. In normal mode, the write signal is delayed by adding wait states into a DMA cycle. But in extended write mode, the write signal is extended earlier without adding wait states.

TC Stop Mode

If the D₆ bit of the mode set register is high, then the selected channel is disabled after the terminal count condition is reached. Thus, it stops further DMA operation on that channel. To enable the channel again, this bit must be reprogrammed.

Auto Load Mode

8257 operates in auto load mode when bit D₇ of the mode set register is high. In this mode, only CH – 2 transferred data; other channels are not used for data transfer. It can be used for repeat block or block chaining operations.

Programming of 8257 DMA Controller

The DMA controller operates in two modes for data transfer between the peripheral and the system memory. These two modes are:

Slave Mode

In this mode, the DMA controller is treated as a peripheral. The following tasks are performed in this mode.

1. The microprocessor selects the DMA controller through the chip select (CS) signal.
2. The microprocessor writes the control word in the mode set register and then reads the status register.
3. The microprocessor writes the starting address and counts into the address register and terminal count register, respectively, by using IOW, and can read the status register using IOR.
4. A₀ – A₃ address lines, working as input to specify registers.
5. A₄ – A₇, MEMW, and MEMR are the output signals and tri-stated.

Master Mode

After initialization, the 8257 in master mode keeps checking for a DMA request, and the following tasks are performed in data transfer.

1. When the peripheral is ready for data transfer, it sends a high signal to DRQ.
2. When the DRQ has been received and the channel enabled, the control logic sets HRQ high.
3. In the next cycle, the microprocessor releases the buses and sends the HLDA signal to 8257.
4. After receiving the HLDA signal, the DMA asserts the AEN signal high.
5. When the entire address A₀ – A₁₅ is available on the address bus, the DMA generates DACK to the peripheral.
6. The DMA controller continues the data transfer by asserting the necessary control signals (IOR, IOW, MEMR, and MEMW) until DACK remains high.
7. At the end of data transfer, the DMA asserts the EOP (End of Process) signal low, which can be used to inform the peripherals that the data transfer is completed. The DMA data transfer can also be terminated by sending a low signal to EOP from outside.

Interfacing of 8257

The figure above shows the interfacing of the 8257 with the 8085 microprocessor. The DMA is used to transfer data bytes between input/output (such as a floppy disk) and system memory at high speed. When a transfer begins, the DMA places the low-order byte on the address bus and the high-order byte on the data bus and asserts AEN (Address Enable) and ADSTB (Address Strobe). These two signals are used to latch the high-order byte from the data bus; thus, it places the 16-bit address on the system bus.

After the transfer of the first byte, the latch is updated when the lower byte generates a carry (or borrow). The above figure shows two latches: One latch to store a high-order address from the data bus by using the AEN and ADSTB signals, and the second latch to demultiplex the 8085 bus and generate the low-order address by using the ALE (Address Latch Enable) signal. The AEN is connected to the OE signal of the second latch to disable the low-order address bus from the 8085, when the first latch is enabled to latch the high-order byte of the address.