Time Delay in Microprocessor

Time Delay in Microprocessor – In real-time applications, such as traffic light control, digital clock, process control, and serial communication, it is important to keep track of time. In some applications, a time delay is required between the execution of two instructions. There are two techniques to design the time delay in a microprocessor.

1. Hardware technique
2. Software technique

For the hardware time delay technique, additional hardware like 8253/8254 (Programmable Interval Timer) is required. The hardware technique has the advantages like it is very accurate. It can be used for real-time applications and frees the microprocessor to perform other tasks at the same time. The fundamental limitation of the hardware technique is the cost.

In the software time delay technique, no additional hardware is required, so it is cheaper than the hardware technique. But it has some limitations, like it is not accurate, makes the microprocessor busy for the entire delay period, etc. The tedious calculation is required to decide the count. The following methods are used to provide a time delay using a software technique.

1. Using the NOP instruction
2. Using counter
3. Using a nested loop

Time Delay using NOP Instruction

Meaning of instruction NOP is NO operation. This instruction does nothing but simply makes the microprocessor busy for 4T states. So by executing a NOP instruction in between two instructions, a delay of 4T states may be provided.

                    1
1T-state = ___________________
           Operating frequency

Let’s take an example question to understand the time delay using the NOP instruction

Number of times the instruction NOP has to be executed to provide a time delay of 1m sec. between two instructions is (1m sec)/(2μ sec) = 500 times. From the above example solution, it is clear that the provided delay using the NOP instruction is not a good solution. This is because the programmer has to store a large number of NOP instructions in memory.

Time Delay using Counter

A counter can be used to provide the time delay. According to this technique, a counter is initialized with the desired value and decremented by one. This looping operation continues till the count value reaches zero. Since the execution times of the instructions used in a counting are known, the initial value of the counter can be determined. The counter can be designed by using a register (8-bit counter) or a register pair (16-bit counter). The figure below shows the flow chart for time delay using a counter.

Using One Register (8-bit counter)

Here, OF = Opcode Fetch and MR = Memory Read

The instruction JNZ is a three-byte instruction. The number of T-states for the JNZ instruction is shown as 10/7 in the program. It means that the microprocessor 8085 requires 10T-states to execute the instruction when the condition is true. But when the condition is false, the loop is terminated, requiring only 7T states. Time delay in the 8-bit counter using one register is given as below:

TDelay = 7T + (n-1)(4T + 10T) + (4T + 7T)
= 7T + 14nT - 14T + 11T
= 7T + 14nT - 3T
TDelay = 4T + 14nT

Let’s take an example question to understand the time delay using a one-register (8-bit Counter)

Using Register Pair (16-bit Counter)

The maximum time delay (1.785 sec.), which can be introduced between two instructions using one register, is not sufficient for some applications. In those applications, we need to initialize the counter more than FFH or 255. Hence, a counter using a register pair instead of one register is used.

Here, OF = Opcode Fetch and MR = Memory Read.

In the above program, the DCX instruction is used to decrement the contents of the DE register pair. This instruction has 6T states in its opcode fetch machine cycle and does not affect any flag. When the contents of the DE register pair reach zero, the zero flag remains unchanged. Therefore, another technique is used to affect the zero flag as shown in programming by performing an ORing operation between the lower and higher pair, as shown below:

TDelay = 10T + (N-1)(6T + 4T + 4T + 10T) + (6T + 4T + 4T + 7T)
= 10T + 24NT - 24T + 21T
TDelay = 7T + 24NT

Let’s take an example question to understand the time delay using the Register Pair (16-bit Counter)

The value of count is 41666₁₀ or A2C2H. The delay loop using a 16-bit counter will be as follows:

Using nested Loop

This technique is also known as time delay using a loop within a loop. In this, there is more than one loop. The outer loop sets the count to repeat the delay provided by the inner loop. A flowchart for time delay using a nested loop is shown in the figure below.

Let’s take an example program to understand time delay using a nested loop.