Programmable Interrupt Controller (PIC) 8259 – Microprocessor

Programmable Interrupt Controller (PIC) 8259 – The 8259 programmable interrupt controller is used to provide additional interrupts other than software and hardware interrupts of the 8085 microprocessor. The 8259 interrupt controller can do the following things :

1. Manage eight interrupts according to the instructions written into its control registers. This is equivalent to providing eight interrupt pins on the processor by connecting to its INTR pin of the 8085 microprocessor. Thus, we have a total of 12 interrupt lines by using one 8259 (8 new and 4 earlier interrupt lines) (TRAP, RST 7.5, RST 6.5, RST 5.5), with the loss of the INTR line.
2. Vector an interrupt request anywhere in the memory map. However, all eight interrupts are spaced at an interval of either four or eight locations. This eliminates the major drawback of the 8085 interrupts, in which all interrupts are vectored to memory locations on page 00H.
3. Provides eight levels of interrupt priorities in a variety of modes, such as fully nested mode, automatic rotation mode, and specific rotation mode.
4. Mask each interrupt request individually.
5. Read the status of pending interrupts, in-service interrupts, and masked interrupts.
6. Be set up to accept either the level-triggered or the edge-triggered interrupt request.
7. Be expanded to 64 priority levels by cascading an additional 8259s.
8. Be set up to work with either the 8085 microprocessor mode or the 8086/8088 microprocessor mode.

Block Diagram of 8259

The figure below shows the internal block diagram of the 8259. It includes eight blocks: control logic, read/write logic, data bus buffer, three registers (IRR, ISR, and IMR), priority resolver, and cascade buffer. The diagram shows all the elements of a programmable device, plus additional blocks.

The functions of these blocks are as follows:

Control Logic

This block has two pins: INT (interrupt) and INTA (interrupt acknowledge). The functions of these are:

1. INT (Interrupt): It is an active high output signal. Whenever a valid interrupt is asserted, this signal goes high. This is connected to the INTR pin of the microprocessor.
2. INTA (Interrupt Acknowledge): It is an active low input signal. The INTA is the interrupt acknowledge signal from the microprocessor. This is connected to the INTA pin of the microprocessor.

Read/Write Logic

Read/Write logic has the following signals:

1. A₀: When the address line A₀ is set to logic 0, the controller is selected to write a command or read a status. This is connected to the A₀ address line of the microprocessor.
2. RD (Read), WR (Write), and CS (Chip select): These pins have their usual functions.

Data Bus Buffer

It has bidirectional data pins (D₀ – D₇). These pins are connected to the data bus of the microprocessor. The data buffer allows the 8085 to send control words to the 8259 and read a status word from the 8259.

Cascade Buffer/Comparator

This block is used to expand the number of interrupt levels by cascading two or more 8259s. The pins associated with this block are:

1. CAS 0 – CAS 2(Cascade lines): These lines are used to connect more than one 8259 in cascade mode.
2. SP/EN (Slave Program/Enable Buffer): It is used to define the 8259 as master/slave. When a single 8259 is used, it operates as a master. Then the SP/EN pin is connected to +5V (logic 1). When more than one 8259 is used, then only one 8259 can be a master. The remaining 8259s must operate as slaves, with SP/EN connected to ground (logic 0).

Registers

8259 has three registers: IRR, ISR, and IMR.

1. IRR (Interrupt Request Register): The Interrupt Request Register (IRR) has eight input lines (IR₀ – IR₇) for interrupts. When these lines go high, the requests are stored in the register.
2. ISR (In-Service Register): The In-Service Register (ISR) stores all the interrupts that are currently being serviced.
3. IMR (Interrupt Mask Register): The Interrupt Mask Register (IMR) stores the masking bits of the interrupt lines to be masked.

Priority Resolver

The priority resolver (PR) examines three registers (IRR, ISR, and IMR). It resolves the priority and generates an INT (high) signal when it finds the interrupt request appropriate.

Operation of Interrupt

1. If lines (IR₀ – IR₇) are high, it means that the request is stored and the corresponding IRR bit is set.
2. All three registers are checked by the priority resolver, and the INT pin is set high.
3. The microprocessor acknowledges the interrupt by sending an INTA pulse.
4. When an INTA pulse is received from the microprocessor, the ISR bit with the highest priority is set, and the corresponding IRR bit is reset. Thereafter, the call instruction code CDH is set on pins (D₀ – D₇). Since all the RST instructions are 1-byte call instruction having some vectored location.
5. Two more INTA signals on the data bus are placed while decoding the CALL instruction.
6. The two INTA pulses are defined as that lower 8-bit address is released at the second INTA pulse, and the higher 8-bit address at the third INTA pulse. It completes the 3-byte CALL instruction.
7. At the third INTA pulse, the ISR bit is reset either automatically with the help of AEOI (Automatic End of Interrupt) or by a command word that should be given at the end of the subroutine, which is determined by the initialization command word.

Priority Modes of PIC

Many types of priority modes are available with 8259. They can be changed dynamically during the program by writing appropriate command words. Priority modes, which are commonly used, are as follows:

Fully Nested Mode

In this mode, the interrupt requests from IR₀ to IR₇ are arranged, from highest to lowest priority. IR₀ has the highest priority, and IR₇ has the lowest priority. When an interrupt is acknowledged, the highest priority request is determined, and its vector location is placed on the bus. Also, any IR can be set to the highest priority.

7 = Lowest priority and 0 = Highest Priority

Automatic Rotation Mode

In some applications, there can be equal priority assigned to no of interrupting devices. With the help of this mode, the interrupt request, after being served, receives the lowest priority.

7 = Lowest Priority

Assuming that IR₂ has just been serviced, it will receive the seventh (lowest) priority.

Specific Rotation Mode

In this mode, the user can select any interrupt request for the lowest priority. The programmer, by programming the bottom priority and fixing other priorities, can change any priority.

Programming the 8259

1. The first INTA pulse is dedicated to CALL, having opcode CDH.

C = D₇ – D₄ and D = D₃ to D₀

2. The second INTA pulse enables the lower address of the service routine on the data bus when interval = 4 bits, A₅ – A₇ are programmed, while A₀ – A₄ are automatically inserted by the 8259. When interval = 8, only A₀ and A₇ are programmed, while A₀ – A₅ are automatically inserted.
3. During the third INTA pulse, the higher address of the service routine as byte 2 of the initialization sequence (A₈ – A₁₅) is enabled onto the bus.

Command Words of PIT

There are two types of command words:

1. Initialization Command Word (ICW)
2. Operational Command Word (OCW)

Initialization Command Word (ICW)

8259 has 4 ICW_s, ICW₁ and ICW₂ are essential whereas ICW₃ and ICW₄ depends upon the types of modes being used.

ICW₁ and ICW₂: The request levels can be programmed to be spaced either at an interval of 4 or at an interval of 8. ICW1 and ICW2 are shown in the table below.

A₁₅ – A₈ = Interrupt Vector Address

ICW₁ provides the following information:

1. Single or multiple 8259s in the system.
2. 4-bit or 8-bit interval between the interrupt vector locations.
3. The address bits A₅ – A₇ of the CALL instruction; the rest are supplied by the 8259, as shown in the two tables below.

CALL ADDRESS = D₀ to D₇

CALL ADDRESS = D₀ to D₇

ICW₂ defines the remaining high-order byte of the call address (A₈ – A₁₅).

ICW₂ and ICW₄: ICW3 is required only when more than one 8259 is used in the system by the cascading process. It is optional and needed when bit D₁ of ICW₁ is 0. Both master and slave will be identified. ICW₄ is also needed only when bit D₀ of ICW₁ is 1.

1 = Slave for IR Input
0 = No slave for interrupt request

Slave Cascade Number = ID₂, ID₁, ID₀

Operational Command Word (OCW)

It has three OCWS. The OCWS are written in the control register after ICWS.

(a) OCW₁: The OCW1 is used to set and reset the mask bits in the interrupt mask register.

(b) OCW₂: The OCW₂ is used to control the rotation (R) and EOI (End of Interrupt) modes and their combination of two. It is used to set various priority levels.

(c) OCW₃: The OCW₃ is used to set and reset the special mask and poll command.

End of Interrupt in PIC

When any interrupt service is completed, it is necessary to reset the corresponding ISR bit to update the information in the ISR. This is called the End-of-Interrupt (EOI) command. It can be issued in three ways:

Non-specific EOI Command

When this command is sent to the 8259, it resets the highest priority ISR bit. The format for non-specific EOI instruction is as follows:

A₀ should be 0 while issuing the EOI instruction.

Specific EOI Command

This command is used to specify which ISR bit is to be reset. The format for specific EOI instruction is as follows:

ISR bit to be reset

Automatic EOI

No command is required to specify End-of-Interrupt. During the third INTA, the ISR bit is reset. The limitation of this mode is that the ISR does not have information on which IR is being serviced. Thus, any IR can interrupt the service routine, irrespective of its priority, if the interrupt enable flip-flop is set.