The 8086 Microprocessor | Architecture | Pin Diagram | Instructions

8086 Microprocessor – The Intel 8086 is a 16-bit microprocessor. The term 16-bit means that its arithmetic logic unit, its internal registers, and most of its applications are designed to work with 16-bit binary words. The 8086 microprocessor, packaged in a 40-pin dual-in-line package, was implemented in N-channel depletion load silicon gate technology. The pin diagram of Intel 8086 is shown in the figure below.

Pin Diagram of 8086

Features of the 8086 Microprocessor

1. The 8086 microprocessor has a 16-bit data bus. It can read data from or write data to memory and I/O ports, either 16-bit or 8-bit at a time.
2. The 8086 microprocessor has a 20-bit address bus. It can address any one of 2²⁰ (1,048,576) memory locations. Each of the 2²⁰ (1M) memory addresses of the 8086 represents a byte-wide location. Sixteen-bit words will be stored in two consecutive memory locations.
3. The 8086 microprocessor can perform bit, byte, word, and string operations with arithmetic and logical operations, including multiply and divide.
4. The 8086 microprocessor has two operating modes: (i) Minimum mode and (ii) Maximum mode.
5. The 8086 microprocessor supports multiprogramming, which means that the code for two or more processes is in memory at the same time and is executed in a time-multiplexed way.
6. The pipelining concept is used in the 8086 microprocessor. The 8086 microprocessor fetches up to six instruction bytes from memory and stores them in a queue.

Architecture of the 8086 Microprocessor

The 8086 microprocessor is divided into two independent functional parts. These two parts are named as follows:

1. Bus Interface Unit (BIU)
2. Execution Unit (EU)

These two functional units can work simultaneously to increase system speed and hence increase the number of instructions executed per unit time. The internal architecture of the 8086 microprocessor is shown in the above figure.

Bus Interface Unit (BIU)

As its name suggests, the BIU provides the interface between the Execution Unit (EU) and memory. The BIU sends out the address of the next instruction to be executed, fetches that instruction from memory, reads data from port and memory, and writes data to port and memory. The primary responsibility of the BIU is to handle all kinds of communication for the Execution Unit (EU).

The BIU has a 16-bit bidirectional data bus and a 20-bit address bus. The BIU performs various interfacing operations with the help of the following:

1. The Instruction Queue
2. Segment Registers
3. Instruction Pointer
4. Address Summer

The Instruction Queue

The BIU fetches up to six instruction bytes for the instructions to be executed. The BIU stores these perfected bytes in a first-in-first-out register set called the instruction queue. It is six bytes long. The instructions from the queue are taken for decoding sequentially. Once a byte is decoded, the queue is rearranged by pushing it out, and the queue status is checked for the possibility of the next opcode fetch.

This is much faster than sending out an address to the system memory and waiting for the memory to send back the next instruction byte or bytes. Fetching the next instruction while the current instruction executes is called pipelining. In case of jump and call instructions (Branching Instructions), the queue must be dumped and then reloaded, starting from a new address.

Segment Registers

The 8086 microprocessor has a 20-bit address bus. So it can address any of 2²⁰ (1M) bytes of memory. However, at any given time, the 8086 works with only four 64KB segments within this IMB range. Each segment has a 16-bit (2¹⁶ = 64K) address. Four segment registers store the address of the respective segment. These segment registers are named as:

1. Code segment register
2. Stack segment register and
3. Data segment register
4. Extra segment register

Instruction Pointer (IP)

The instruction pointer holds the 16-bit address of the next instruction code byte within the code segment. The contents of the IP are actually the offset from the code segment’s base address. The code segment register points to the base of the code segment. The instruction pointer contains the distance or offset from this base address to the next instruction byte to be fetched.

Address Summer

The BIU of the 8086 microprocessor has a 20-bit address bus. It means the actual address must contain 20 bits. But the base address of segments (stored in the segment register) and the offset address (stored in the instruction pointer) are only 16 bits. The 20-bit physical address is formed from the base address and offset address using an address summer.

Execution Unit (EU)

The execution unit of the 8086 microprocessor instructs the BIU to fetch the instruction or data, decode the instruction, and execute instructions. The execution unit has the following blocks:

1. Control System
2. Instruction Decoder
3. Arithmetic Logic Unit (ALU)
4. Flag Registers
5. General Purpose Registers
6. Pointers and Index Registers

Control System

The execution unit of the 8086 microprocessor contains a control system to perform internal operations. The circuitry of the control system provides signals to the internal operations.

Instruction Decoder

The instruction decoder in the EU finds the meaning of the instruction. In other words, an instruction decoder translates the fetched instruction into a sequence of actions that the EU carries out.

Arithmetic Logic Unit (ALU)

The arithmetic logic unit (ALU) in the EU of the 8086 microprocessor can perform addition, subtraction, increment, decrement, multiplication, division, ANDing, ORing, XORing, etc. The ALU can perform 16-bit arithmetic and logic operations on data.

Flag Register

The flag register is used to indicate the status of the result after any operation. The EU of the 8086 microprocessor contains a 16-bit flag register that contains nine active flags. Six of them are used to indicate some condition produced by instructions and are called conditional flags, and the remaining three are named control flags. The flag register is shown in the figure below.

The flags of the flag register are as follows:

1. Carry Flag: The carry flag serves as a carry or borrow status produced by the addition or subtraction operation. The carry flag shows that there is a carry or borrow beyond the most significant bit (MSB).
2. Parity Flag: The parity flag shows whether the number of ones in the lower byte is even or odd. It shows P = 1 if the number of ones in the lower byte is even; otherwise, P = 0 if the number of ones in the lower byte is only odd.
3. Auxiliary Flag: If there is any carry from the D₃ bit to the D₄ bit, the auxiliary flag will be set. This flag is not available to programmers.
4. Zero flag: The zero flag shows whether the result of the operation is zero or not. If the result contains all zeros, the zero flag will be set, otherwise reset.
5. Sign flag: Sign flag is a replica of D₇, the bit of the result.
6. Overflow flag: The overflow flag is used for signed operations. It is set whenever the sign bit is modified. This indicates that the result is out of range.
7. Trap flag: It is a control flag. It is used to interrupt the program execution after each step, when set. The trap flag is used for single-step execution of a program. Hence, it plays an important role in debugging.
8. Interrupt flag: By setting and resetting the interrupt flag, the interrupts can be enabled and disabled, respectively.
9. Direction flag: This flag is used with string operations. If the direction flag is reset, the string is processed from its beginning, with the first element having the lowest address. Otherwise, if the direction flag is set, the string is processed from the high address towards the low address.

General Purpose Registers

The execution unit has four general-purpose 16-bit registers named AX, BX, CX, and DX. These registers can also be used for 8-bit temporary storage registers labeled as AH, AL, and BH. BL, CH, CL, DH, and DL. The AL register is also named the accumulator. 16-bit data can be stored in the specified combination of two registers. The acceptable register pairs are AH-AL, BH-BL, CH-CL, and DH-DL. The AH-AL pair is referred to as the AX register. The BH-BL pair is referred to as the BX register, the CH-CL pair is referred to as the CX register, and DHDL. The pair is referred to as the DX register.

Pointers and Index Registers

The 20-bit address of memory locations is divided into two parts: the base address and an offset address. Base address is stored in the segment register, whereas the offset address is stored in a pointer or in an index register. The offset address is stored in the following register:

1. Stack Pointer (SP): It is used as the offset register for the stack segment. It functions similarly to the 8085 microprocessor
2. Source Index (SI): It is used as the offset register of the source data byte in the data segment for string operations.
3. Destination Index (DI): It is used as the offset register of the destination data byte in the extra segment for string operations.

Operating Modes of 8086 Microprocessor

There are two modes of operation for the 8086 microprocessor, namely the minimum mode and the maximum mode. The operating mode of the 8086 is determined by the logic level applied to the MN/MX input (Pin 33). If pin 33 is asserted high, then the 8086 will function in minimum mode, whereas if pin 33 is low, the 8086 will be in maximum mode.

Minimum Mode

Minimum mode operation is obtained by connecting the mode selection pin MN/MX (pin 33) to high (+ 5.0V). When only one microprocessor, 8086, is to be used in a microprocessor-based system, the minimum mode is selected. In this mode, pins 24 through 31 will have the functions shown in parentheses next to the pins as shown in the pin diagram. The minimum mode operation of the 8086 is shown in the figure below. This system is cheaper because all the control signals for the memory and I/O are generated by the microprocessor itself. The control signals are identical to those of the 8085 microprocessor.

Maximum Mode

The maximum mode of the 8086 microprocessor is obtained by connecting the mode selection pin MN/MX to low (OV). The maximum mode is used when a multiprocessor system is designed. In this case, operation control signals are issued by an external bus controller, which is used with the 8086 for this very purpose. There are not enough pins on the 8086 for bus control during maximum mode because new pins and new features have replaced some of them. The maximum mode operation of the 8086 is shown in the figure below.

Pins and Signals of the 8086 Microprocessor

The 8086 microprocessor is a 16-bit microprocessor packaged in a 40-pin CERDIP or plastic package. The pin diagram of 8086 is shown above at first. Since the 8086 microprocessor operates in two modes, some pins serve different functions in single-processor (minimum) mode and in multiprocessor (maximum) mode. The 8086 signals can be categorised into three groups:

1. Common signals (both minimum and maximum mode)
2. Signals for minimum mode
3. Signals for maximum mode

Common Signals

These signals are available on the specified pins of the 8086 microprocessor. These do not depend on the operating mode of the 8086 microprocessor.

AD₀-AD₁₅: These are time-multiplexed address and data lines. In the first T-state of the machine cycle (ALE = 1), the memory address is available on these lines; later on, these lines can be used for data transfer.

A₁₉/S₆, A₁₈/S₅, A₁₇/S₄, A₁₆/S₃: These are time-multiplexed address and status lines. During the first T-state, these lines contain the high-order address of the memory. Status information, which identifies the type of operation being done in that cycle, is sent out on these lines during the later part of the cycle.

BHE/S₇ (Bus High Enable/Status): The bus high enable signal is used to indicate the transfer of data over the high-order (D₈ – D₁₅) data bus. It means an 8-bit device connected to the upper half of the T-state. It is multiplexed with the status signal S₇. During the later part of the machine cycle S₇, a signal is available at this pin.

RD (Read): This signal is used for the read operation. It is an active low signal and when low, indicates to the peripheral that the 8086 is performing a memory or I/O read operation.

READY: This is an input active high signal. This is the acknowledgement signal from the slower device to indicate the completion of data transfer. If it is high, it indicates that the peripheral is ready for the next data transfer.

RESET: This input signal causes the system to be reset. This is an active high and must be active for at least four clock cycles. When it is active, the program execution starts from FFFFOH.

CLK: The clock input provides the basic timing for the microprocessor operations. The range of frequency for different 8086 versions is from 5MHz to 10MHz.

INTR (Interrupt Request): This is a level-triggered input signal. This is an active high signal and internally synchronized. This can be internally masked by resetting the interrupt enable flag.

NMI (Non Maskable Interrupt): This is an edge-triggered input signal. The NMI can not be ignored or masked internally by software instructions. A transition from low to high initiates the interrupt response at the end of the current instruction. This is internally synchronized.

TEST: This is an active low input signal that is examined by a ‘WAIT’ instruction. If the TEST input goes low, the execution will continue; otherwise, the processor remains in an idle state.

MN/MX: The level of this pin decides the operating mode of the 8086. When this pin is high, the microprocessor operates in minimum mode, whereas when it is low, the microprocessor operates in maximum mode.

V_cc: 5V power supply for the operation of the internal circuit.
GND: Ground for the internal circuit.

Signals for Minimum Mode

If pin 30 (MN/MX) is asserted high, then the 8086 will function in minimum mode, and pins 24 through 31 will have the functions shown in parentheses next to pins as shown in the pin diagram.

M/IO (Memory/Input-output): When it is high, the microprocessor accesses the memory. When it is low, the microprocessor accesses the input/output device. This line becomes active in the first T-state and remains active till the last T-state (T₄) of the current machine cycle.

INTA (Interrupt Acknowledgement): It is an active low output signal. This signal is issued by the microprocessor in response to the received interrupt signal. It means that when it is low, the microprocessor has accepted the interrupt request.

ALE (Address Latch Enable): This signal is used to demultiplex the address data bus. It goes high during the first T-state (T₁). The microprocessor sends this signal to latch the address from the address data multiplexed bus.

DT/R (Data Transmit/Receive): This output signal is used to decide the direction of data flow through the trans receiver (bidirectional buffer). When the microprocessor sends out data, this signal is high, and when the microprocessor is receiving data, this signal is low.

DEN (Data Enable): This signal is an indication of the availability of valid data over the address/data lines. It is used to enable the trans receiver to separate the data from the multiplexed address/data signal.

WR (Write): This signal is used for write operation. It is an active low signal and when low, indicates to the peripheral that the 8086 is performing a memory or I/O write operation.

HOLD: When another device in a microprocessor-based system wants to use the address and data bus, it sends a HOLD request to the microprocessor through this pin. It is an active high signal.

HLDA (Hold Acknowledgement): It is issued by the microprocessor in response to the HOLD signal. It is an active high signal and goes low when the HOLD request is removed.

Signals for Maximum Mode

If the MN/MX pin is asserted low, then the 8086 is in maximum mode. This mode is used for the multiprocessor system.

QS1, QS0 (Queue Status): These lines give information about the status of the prefetched queue of BIU. The table below shows various queue statuses.

LOCK: It is an active low-output signal. It indicates that other system bus masters will be prevented from obtaining the system bus access, while the LOCK is low. It is activated by the LOCK prefix instruction and remains low until the completion of the next instruction.

S₂, S₁, S₀ (Status Lines): These are status lines that reflect the type of operation being carried out by the microprocessor. These signals are connected to the bus controller 8288. The bus controller generates memory and I/O access control signals. The table below shows the logic for status signals.

RQ/GT₀, RQ/GT₁ (Request/Grant): These pins are used by other local bus masters to force the processor to release the local bus at the end of the current cycle. These pins are used as input/output (bidirectional) pins. A low input signal is used for the request, and the low output signal gives a grant.

8086 Memory Management and Physical Address

The 8086 BIU sends out 20-bit addresses, so it can address any of 2²⁰ (1M) bytes in memory. The whole 1MB memory of the 8086 is divided into 16 segments with a maximum capacity of 64KB. As discussed in the flag register, out of these sixteen segments, four are user-defined and can be used by the programmer.

Segments: There are four segments used in the whole 1MB memory. The four segments are shown in the figure below.

1. Code Segment: This segment is used to store the program code.
2. Data Segment: This segment is used to store the input and output data for the program.
3. Stack Segment: This segment is used as a stack for temporary storage
4. Extra Segment: The extra segment is used to store the data if the data ranges more than 64KB.

The memory segmentation can be overlapped and non-overlapped.

Segment Address: Four segment registers in the BIU are used to hold the upper 16 bits of the starting addresses of four memory segments. Segment addresses are user-defined so that the segments can overlap for small programs. The segment can begin at any memory address that is divisible by 16.

The segment registers are named as follows:

1. Code Segment Register
2. Data Segment Register
3. Stack Segment Register
4. Extra Segment Register

Each segment register stores the base or starting address of the respective memory segment.

Offset Addresses: The offset address is the effective address that contains the displacement from the base (starting) address of the memory segment being used. This is a 16-bit address and is stored by the programmer in pointer and index registers. The six different registers, named Base Pointer (BP), Stack Pointer (SP), Instruction Pointer (IP), Source Index (SI), Destination Index (DI), and BX, store the offset address. In some instructions, it can be defined directly with a 16-bit address.

The table below shows the segments and their default pointers to form a pair of bus and effective address to form a 20-bit physical address.

Physical Address: The physical address is a 20-bit read address that is formed in the address summer by using the corresponding 16-bit segment address (base address) and its respective 16-bit offset address. This is formed by rotating the segment address by 4 bits towards the left side and adding it to the offset address directly.

Advantages of Memory Segmentation

Dividing the whole 1MB memory of the 8086 microprocessor into segments (each 64KB in size) is called memory segmentation of the 8086 microprocessor. The memory segmentation provides the following advantages:

1. With the segmentation, the 8086 microprocessor has to manipulate and store only a 16-bit address instead of 20 bit.
2. Searching and accessing memory locations become faster and easier.
3. Since data is stored in different areas of memory, each time the program is executed, it can be relocated. This is a very useful feature of multi-programming.