Interrupt in Microprocessor

Interrupt in Microprocessor – In general, the microprocessor executes the instructions in a sequence to complete the specific task. Sometimes it is needed to break the sequence of the program at the demand of an external device. This can be achieved by an interrupt signal. An interrupt is defined as a signal that is generated by a peripheral to break the sequence of the main program, and program execution jumps to the pre-specified memory location.

A subroutine is written at the predefined memory location to complete the task provided for the peripheral. This subroutine is named the Interrupt Service Routine (ISR). An interrupt service routine is similar to a subroutine. The difference is that a subroutine is called by a CALL instruction, and this is known to the programmer at what time the subroutine is to be called, but an interrupt service routine is called in response to an interrupt signal and thus is not known by the programmer at what time it is to be called.

If more than one peripheral is connected to a microprocessor system, any one of them may demand service at any time. The one way to provide services to all peripherals is for the microprocessor to continuously check all the peripherals one by one. If any peripheral wants the service it will provide, otherwise, check for the next peripheral. This is known as a polling check. The other way allows the microprocessor to execute the main program. The peripheral that wants the service generates a signal to break the execution of the main program. In response to this signal, the microprocessor provides the service to that peripheral. This is known as an interrupt check.

An example of the interrupt concept in the real world is the classroom, where the professor will serve as the microprocessor and the students as peripherals. The classroom scenario for this interrupt analogy will be as follows

Step-1: The professor is busy writing on the blackboard and delivering his lecture. All the students are allowed to ask a query,

Step-2: After writing one line on the blackboard, the professor checks if someone wants to ask a query.

Step-3: The student raises his hand when he wants to ask a question.

Step 4: The professor then completes his sentence, inserts a book mark on book, and acknowledges the student’s request by saying “Yes’.

Step-5: After acknowledgement from the professor, no other student is allowed to ask any other query. Now the student asks the query, and the professor replies to the query.

Step-6: The professor may or may not allow other students to ask a question in between his reply, but he has to reply if the principal comes in class room and asks something. After giving a reply, all students are allowed to ask queries.

Step-7: The professor goes back to the book, finds the bookmark, and starts writing on the blackboard and delivering his lecture.

The 8085 microprocessor interrupt process can be described in terms of seven steps.

Step-1: The microprocessor is busy executing the main program. Using the software instruction (Enable Interrupt – El), all peripherals are allowed to interrupt the microprocessor.

Step-2: After executing each machine cycle, the microprocessor checks the INTR (Interrupt Request) pin.

Step-3: The peripheral generates an interrupt signal and send to the INTR pin of the microprocessor when it wants the service from the microprocessor.

Step 4: The microprocessor completes the execution of the current instruction, saves the address of the next instruction of the main program, and sends an acknowledgement signal on the INTA pin of the microprocessor.

Step-5: After the interrupt acknowledgement signal (INTA), no other interrupt request is accepted. The microprocessor provides the service to the peripheral.

Step-6: While providing the service to the peripheral, the microprocessor may or may not respond to other interrupt requests from other peripherals. There is one interrupt (TRAP discussed later) to which the microprocessor has to respond. After providing the service to the peripheral, the microprocessor enables all interrupts using a software instruction.

Step-7: The microprocessor returns to the main program after retrieving the address that is stored in step-4.

Classification of Interrupts in a Microprocessor

The interrupt signal is generated by a peripheral. The microprocessor can respond to or discard the request as per the priority between the current ongoing operation and the requesting operation. The 8085 microprocessor interrupts can be classified into two categories.

1. Software Interrupt
2. Hardware Interrupt

Software Interrupt

The interrupt caused by executing special interrupt instructions is called a software interrupt. After execution of these instructions, the microprocessor completes the execution of the instruction it is currently executing and transfers the program control to the subroutine program. After completing the execution of the subroutine, the program control returns to the main program.

The 8085 microprocessor instruction set includes 8 RST (Restart) instructions. These instructions are executed in a similar way to CALL instructions. Whenever RST instruction is executed, the address in the program counter (PC) is stored in the stack before the program execution is transferred to the RST call location. When the program encounters the RET instruction in the interrupt service routine, the program control returns to the main program. The returning address is restored from the stack.

The fundamental differences between CALL and RST instructions are as follows:

1. The CALL instruction specifies the address (e.g., CALL 7050H), whereas for RST instructions, the locations are predefined on page 00H of memory.
2. The programmer decides the execution of the CALL instruction by writing the instruction in the program. Whereas the execution of RST instructions is decided by the peripheral by inserting the hex code for the RST instruction into the data bus.

The table below shows various RST instructions, their codes in binary as well as in hexadecimal, and their call locations.

Binary Code = D₇ – D₀

The 8085 microprocessor has eight software interrupts from RST 0 to RST 7. The hex code for them depends on the bits D₅, D_4, and D₃. All other bits are always set. The hex code for these interrupts can be calculated by writing the binary equivalent of the interrupt number in three bits (D₅, D_4, and D₃). In a similar manner, the vector address for these interrupts can be calculated by multiplying the interrupt number by 8₁₀.

Hardware Requirements – The execution of RST instructions is decided by the peripheral by inserting the hex code into the data bus. The hex code of the RST instruction is inserted with the help of a tri-state buffer. An additional hardware circuit to implement the instruction RST 5 is shown in the figure below.

Whenever the microprocessor sends an interrupt acknowledgement (INTA) to the peripheral, it activates the tri-state buffer. The data (EEH) at the input goes to the output of the tri-state buffer and enters the data bus.

Timing Diagram for RST Instruction

The RST instructions are executed in a similar way to that of the CALL instruction, with a one-byte length. Since RST instructions have a one-byte length, the read cycle has only one machine cycle, i.e, opcode fetch. After reading the RST instruction, the microprocessor stores the address of the next instruction into the stack.

This is a memory-related writing operation. Therefore, two memory write machine cycles are required. The above figure shows the timing diagram of any RST instruction. This includes opcode fetch and two memory write machine cycles.

Hardware Interrupt

The types of interrupts where microprocessor pins are used to receive interrupt requests are called hardware interrupts. The 8085 microprocessor has five pins for receiving external interrupt signals. These pins are named TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR. Hardware interrupts can be further classified into different categories on the basis of different criteria, such as

1. Vectored and Non-Vectored Interrupts
2. Maskable and Non-Maskable Interrupts

Vectored and Non-Vectored Interrupts – Whenever a peripheral interrupts the microprocessor, the microprocessor breaks the sequence of the main program, and program control jumps to the predefined memory location. The predefined memory location is the starting address of the interrupt service routine (ISR). The predefined address of memory is known as a vector address, and such interrupts are known as vectored interrupts.

All those interrupts for which vector location is not predetermined or is determined by some additional external means are known as non-vectored interrupts. Out of five hardware interrupts, only one (INTR) is a non-vectored interrupts, other remaining four are vectored interrupts. The vector location for the vectored interrupt and the subroutine location for the non-vectored interrupt are shown in the table below.

The subroutine location for the INTR interrupt is determined by externally connected hardware, and this location can be one of eight locations, as shown in the table below.

Maskable and Non-Maskable Interrupts – Maskable interrupts are the interrupts that can be ignored by the microprocessor. Maskable interrupts can be enabled and disabled under program control. Whenever these interrupts are masked using an appropriate technique, the microprocessor does not respond to the respective interrupt request signal and continuously executes the main program.

The interrupts that can not be masked under software control are called non-maskable interrupts. TRAP is the only non-maskable interrupt of the 8085 microprocessor. This interrupt is used for critical events such as power failure and emergency shut-off. The maskable and non-maskable hardware interrupts are shown in the table below.

Interrupt Structure

The 8085 microprocessor has five interrupts: TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR. Whenever any interrupt pin of the microprocessor (except the INTR pin) is activated by the peripheral, the execution of the program jumps to the predefined memory location. The predefined location is the starting address of the service routine for the respective interrupt. The interrupt structure is shown in the figure below. In the 8085 microprocessor, when a logic signal is applied to a maskable interrupt input, the microprocessor is interrupted only if that particular interrupt is enabled. The figure below indicates that the 8085 microprocessor is designed to respond to edge triggering, level triggering, or both.

TRAP Interrupt

TRAP is a non-markable interrupt. This is also known as NMI. It is unaffected by any mask or interrupt enable. The TRAP is both a positive-edge and level-triggered interrupt. It has the highest priority among all the interrupts. When the TRAP signal is recognised by the microprocessor, the interrupt acknowledgement signal (INTA) is sent to the peripheral. The microprocessor completes the current execution and pushes the address of the next instruction of the main program into the stack.

Now the program counter is loaded with the fixed vector address 0024H. The microprocessor now starts execution from memory location 0024H, which is the starting address of the service routine corresponding to the TRAP interrupt.

RST 5.5 and RST 6.5

The hardware interrupts RST 5.5 and RST 6.5 are level-triggered signals. Both are maskable interrupts. It means these can be ignored by the microprocessor if masked. Once the 8085 microprocessor accepts the interrupt, RST 5.5 or RST 6.5. It generates the acknowledgement signal (INTA) and sends it to the peripheral. The microprocessor completes the current execution, pushes the address of the next instruction into the stack and loads the program counter with the corresponding vector address. The vector address for RST 5.5 is 002CH, and for RST 6.5, it is 0034H.

RST 7.5

The interrupt RST 7.5 is a positive-edge-triggered interrupt. It is a maskable interrupt and can be masked through appropriate software and hardware techniques. The vectored address corresponding to interrupt RST 7.5 is 003CH. Whenever the interrupt RST 7.5 is recognised, the microprocessor sends an acknowledgement to the peripheral, stores the address of the next instruction into the stack and jumps to the vectored address 003CH by loading the program counter.

INTR (Interrupt Request)

It is a non-vectored maskable interrupt. It has the lowest priority among all the hardware interrupts. The interrupt request (INTR) is a level-triggered interrupt. Since it is a non-vectored interrupt, additional hardware is required to determine the address of the interrupt service routine. In response to the INTA signal, the additional hardware places an instruction opcode on the data bus.

After receiving the instruction opcode, the 8085 microprocessor stores the address of the next instruction into the stack and executes the received instruction. The table below shows the summary of hardware interrupts in the 8085 microprocessor.

Interrupt Related Instructions

The 8085 microprocessor has four interrupt-related instructions (except RST instructions).

El (Enable Interrupt)

The El instruction sets the interrupt enable flip-flop, enabling the interrupt process. Interrupt enable flip-flop is internal to the microprocessor and plays an important role in masking of interrupts. If the EI instruction is not executed in the program, the program will not respond to any interrupt except the TRAP interrupt.

Note: When any interrupt is acknowledged, the interrupt enable flip-flop resets and disables all interrupts. To enable an interrupt for further processing, it is necessary to execute the instruction El within the interrupt service routine.

DI(Disable Interrupt)

The DI instruction resets the interrupt enable flip-flop and disables the interrupt process. In some applications, the main program is important and must not be disturbed by the peripherals. In such cases, DI instruction disables RST 7.5, RST 6.5, RST 5.5 and INTR interrupts.

SIM (Set Interrupt Mask)

As the name suggests, this instruction is used to set the interrupt mask. This is a 1-byte instruction and operate on the data stored in the accumulator. This is necessary to load appropriate contents in the accumulator before the execution of the SIM instruction. The SIM instruction bit pattern is shown in the figure below.

1. The first function is to set or reset the mask for RST 7.5, RST 6.5 and RST 5.5 interrupts. This instruction reads the contents of the accumulator and sets or resets the interrupts according to the contents of the accumulator (bits D₂, D₁, and D₀). If it contains 1, the corresponding interrupt will be masked; otherwise, available. These bits (D₂, D₁, and D₀) will be taken only when the MSE (Mask Set Enable) bit, D₃, is set (1). If the MSE bit is reset, it will not check the masking bits.
2. The second function is to set or reset the RST 7.5 flip-flop by bit D₄ (R 7.5). If D₄ = 1, RST 7.5 is reset, regardless of whether or not RST 7.5 is masked. This is used to ignore RST 7.5 without servicing it.
3. The third function is to implement serial input/output. If the D₆ bit is set, it enables the serial output operation, and the D₇ bit is transmitted through the serial port (SOD pin). If the D₆ bit is reset, it simply ignores the D₇ bit.

RIM (Read Interrupt Mask)

The RIM instruction is used to read the interrupt status. This is a 1-byte instruction and stores the status in the accumulator. Thus, the status of interrupts can be checked by examining the contents of the accumulator after executing the RIM instruction. The RIM instruction bit pattern is shown in the figure below.

The RIM instruction can be used for the following functions.

1. Read the interrupt mask status (whether masked or available) and load it into the accumulator (D₀, D₁, and D₂).
2. Identify pending interrupts. Since there are several interrupt pins in the 8085 microprocessor, when one interrupt request is being served, other interrupt requests may occur and remain pending. These pending interrupts can be checked through the RIM instruction.
3. Receive serial data. Whenever RIM instruction is executed, the data bit available at the serial input port (SID pin) will be loaded to the D₇ bit of the accumulator.

Interrupt Processing

The interrupt process allows the microprocessor to respond to external requests for attention or service on a demand basis, leaving it free to perform other tasks. The 8085 microprocessor has five hardware interrupts. The microprocessor responds to the interrupt signal received on the pins according to the corresponding interrupt.

TRAP Interrupt

TRAP is a non-maskable, vectored interrupt. It has the highest priority among all the interrupt requests. The following steps occur for the TRAP interrupt.

1. The TRAP interrupt signal is sensed if it changes from low to high and remains high until it is acknowledged.
2. The microprocessor completes the current instruction execution.
3. The address of the next instruction from the program counter is pushed into the stack.
4. The program counter is loaded with the vector location 0024H, and the microprocessor starts execution of the service routine for the TRAP interrupt.
5. In the last service routine, it has a RET instruction. The returning address is retrieved from the stack, and program control returns to the main program.

RST 7.5 Interrupt

RST 7.5 is a maskable, vectored interrupt. It has the second-highest priority after the TRAP interrupt. The following steps occur for the RST 7.5 interrupt.

1. RST 7.5 is a positive edge-triggered interrupt. It is sensed when the interrupt signal goes from low to high. It is stored in a D flip-flop.
2. The microprocessor executes the current instruction completely.
3. The microprocessor checks the bit D₄ (R7.5) and bit D₂(M7.5) of the SIM instruction and interrupt enable flip-flop (IF). If bit D₄ = 0, bit D₂ = 0 and IF = 1, then it generates an acknowledgement signal and resets the interrupt flag.
4. The address of the next instruction from the program counter is pushed into the stack.
5. The program counter is loaded with the vector location 003CH, and the microprocessor starts execution of the service routine for the RST7.5 interrupt.
6. In the last service routine, the RET instruction retrieves the returning address from the stack and program control returns to the main program.

RST 6.5 and RST 5.5 Interrupts

These interrupts are maskable, vectored interrupts. There are level-triggered interrupts. Following steps occur for RST6.5 and RST 5.5 interrupts :-

1. Since RST 6.5 and RST 5.5 are level-triggered, these are sensed if the interrupt request remains high until it is internally acknowledged.
2. The microprocessor completes the current instruction execution.
3. The microprocessor checks the related masks (M6.5 and M5.5) and the interrupt enable flip-flop. If related masks are disabled and the interrupt enable flip-flop is set, an acknowledgement signal is generated, and the interrupt enable flip-flop is reset.
4. The address of the next instruction from the program counter is pushed into the stack.
5. The program counter is loaded with the vector location 002CH (for RST 6.5) or 0034H (for RST 5.5), and the microprocessor starts execution of the service routine.
6. In the last service routine, the RET instruction retrieves the returning address from the stack and program control returns to the main program.

INTR Interrupt

It is a maskable, non-vectored interrupt. The subroutine location is determined by the external hardware used in the interrupt structure. It is a level-triggered interrupt. The following steps occur for the INTR interrupt.

1. Since it is level-triggered, it is sensed if the interrupt request remains high until it is acknowledged.
2. The microprocessor completes the current instruction execution.
3. If the interrupt enable flip-flop is enabled, then the interrupt acknowledgement signal (INTA) is generated. The interrupt enable flip-flop is disabled.
4. The interrupt acknowledgement (INTA) signal is used to insert an RST instruction through external hardware.
5. When the microprocessor receives the RST instruction, it stores the address of the next instruction from the program counter to the stack.
6. The program counter is loaded with the subroutine location specified by the external hardware, and the microprocessor starts execution of that subroutine.
7. In the last subroutine, the RET instruction retrieves the returning address from the stack and program control returns to the main program.

RST Instruction As Break Point – The RST instruction is inserted by the external hardware when an interrupt is requested to INTR. But RST instruction is a software instruction and has its own hex code. Therefore, RST instructions can be used in a program directly by writing the opcode of the RST instructions. Whenever RST instruction is executed, the microprocessor stores the address of the next instruction and transfers the program control to the predetermined location. A service routine may be stored at the predetermined location to complete the specific task.

A breakpoint is an instruction where the execution of the program stops temporarily. This can be achieved with the help of the RST instruction. A service routine is stored at the predetermined RST location. The service routine allows examining the register or memory contents when specified keys are pressed. The RST instruction can be used as a breakpoint, and the corresponding service routine is known as the breakpoint routine. After the break point routine, the program should return to executing the main program at the breakpoint. The breakpoint routine allows the user to test the programs in small parts. For example, if RST 1 is used as a breakpoint, the breakpoint routine is written at the memory location 0008H. Whenever the RST 1 instruction is executed, the program control is transferred to 0008H. Now the user is allowed to check the register or memory contents.