The Intel MMX Architecture & Features

Intel MMX Architecture – The Intel MMX (Multimedia Extension) technology was introduced to improve the 2-D and 3-D imaging for multimedia applications. Most of the algorithms in multimedia applications involve operations on several pixels (picture cells) simultaneously. The Pentium MMX is the next in the Pentium series.

Intel provides the SIMD (Single Instruction Stream Multiple Data Stream) architecture through a set of 57 MMX instructions. This architecture is required by most of the multimedia applications, which involve image processing algorithms and image compression techniques. Conventional microprocessors can operate on two pixels at the most concurrently, but using the MMX instruction set, the processor can load 8 pixels simultaneously and perform concurrent operations on them.

The Intel MMX Architecture

The Intel MMX Architecture has eight general-purpose floating-point registers (80-bit wide) in the floating point unit. For floating point operations, 64 bits are used for the mantissa and the remaining 16 bits for exponential. Intel MMX instructions use these floating point registers as MMX registers and use only the 64-bit mantissa portion of these registers to store MMX operands. Therefore, the MMX programmers virtually get eight new MMX registers, each of 64 bits. Since the MMX registers are all 64-bit long, one can pack a total of 8-pixel values (every 8 bits) in a single register.

Features of MMX

The following features are added using the MMX technology

1. The MMX technology adds 57 new instructions to the instruction set. These instructions are known as enhanced MMX instructions and are designed for performing multimedia tasks.
2. Using MMX technology, any X86 microprocessor can manipulate eight pixels, packed in a single 64-bit register, concurrently.
3. SIMD (Single Instruction Stream Multiple Data Stream) kind of architecture is supported by MMX technology.
4. MMX instruction set helps the programmer to write efficient programs for image filtering, image enhancement, coding, and other algorithms.