Programmable Interval Timer (PIT) 8253/8254 – Microprocessor

Programmable Interval Timer (PIT) 8253/8254 – The 8253/8254 programmable interval timer is similar to software-designed counters and timers. An accurate time delay can be generated by both 8253 and 8254. Software techniques for the generation of time delays are not accurate and make the microprocessor busy in a delay loop. Thus, to overcome this difficulty, additional hardware in the form of 8253/8254 is used.

8253/8254 can be used for applications such as a real-time clock, an event counter, a digital one-shot, a square wave generator, and a complex waveform generator. The 8254 includes three identical 16-bit counters that can operate independently in any one of the six modes. It is packaged in a 24-pin DIP and requires a single +5V power supply. To operate a counter, a 16-bit count is loaded in its register and, on command, begins to decrement the count until it reaches 0. At the end of the count, it generates a pulse that can be used to interrupt the MPU. The counter can count either in binary or BCD.

8254 is an upgraded version of the 8253, and they are pin-compatible. The features that differ for both devices are –

1. The 8254 can operate with a higher clock frequency range (DC to 8MHz), and the 8253 can operate with a clock frequency range (DC to 2MHz).
2. The 8254 includes a status read-back command that can latch the count and the status of the counters.

The pin diagram of 8254 is shown in the figure below.

Block Diagram of the 8253/8254 PIT

Below given figure is the block diagram of the 8254; it includes three counters (0, 1, and 2), a data bus buffer, read/write control logic, and a control register. Each counter has two input signals (CLK and GATE) and one output signal (OUT).

Data Bus Buffer

This tri-state, 8-bit, bidirectional buffer is connected to the data bus (D₀ – D₇) of the microprocessor. The data bus buffer has the following basic functions:

1. Programming the 8253/8254 in various modes
2. Loading the counter register
3. Reading the count value

Control Logic

The control section has five signals.

1. RD (Read): It is an active low signal that is used to read the value of the counters. For peripheral-mapped I/O mode, it is connected to the IOR signal, and for memory-mapped I/O mode, the MEMW signal is connected to this pin.
2. WR (Write): It is an active low signal that is used to write commands or data into counters or control registers. For peripheral mapped I/O mode, the IOW signal is connected to this pin, and for memory mapped I/O mode, the MEMW signal is connected to this pin.
3. A0, A1: Microprocessor address lines A₀ and A₁ are connected to these pins. A combination of these two pins is used to identify various counters and control registers.
4. CS (Chip Select): It is an active low signal to make chip select logic; address lines other than A₀ and A₁ may be used in any combination. If the signal at this pin is low, then the 8253/8254 will function; otherwise, it will not.

Counters

The chip 8253/8254 includes three 16-bit counters, namely: counter 0, counter 1, and counter 2. These are presettable down counters. Each counter has its own 16-bit counter register to set the count value for the respective counter. The following signals are related to these counters.

1. CLK 0, CLK 1, CLK 2 (Clock Signal): These are input signals for counter 0, counter 1, and counter 2, respectively. To generate a delay, the contents of the respective counters are decremented on each clock cycle.
2. GATE 0, GATE 1, GATE 2 (Gate Signal): These are input signals for counter 0, counter 1, counter 2, respectively. To start and stop counting of the respective counter, the GATE signal is used. When the GATE signal is high, the counting starts, and when it goes low, the counting stops.
3. OUT 0, OUT 1, OUT 2 (Output Signal): These are output signals for counter 0, counter 1, and counter 2, respectively. The OUT signal goes high when the contents of a counter reach zero. It can be used as an interrupt signal for a microprocessor to indicate that the counting has been completed.

Power Supply

1. V_cc – It is connected to +5V.
2. GND – It is connected to 0V.

Control Word Register

This register is selected when line A₀ and A₁ are a logic 1 (A₀A₁ = 11). It is used to write a command word which specifies the counter to be used, its mode, and either a read or a write operation. The control word format is shown in the figure below.

SC = Select counter

RW – Read/Write

M – Mode

BCD

Note: Don’t care bits (x) should be 0 to ensure compatibility with future Intel products

Modes of Operation of 8253/8254

The 8253/8254 can operate in six different modes by writing a suitable control word. These modes are described below:

Mode 0: Interrupt on terminal count

1. Initially, the output will be low after the mode set operation.
2. After the count is loaded into the count register, the output will remain low, and the counter will count.
3. When the counter reaches zero, the output will go high and remain high until the count is reloaded. This can be used as an interrupt signal to a microprocessor.

The condition to enable counting is GATE = 1. The following figure shows that the counting (m = 4) is temporarily stopped when the GATE is disabled, and counting starts again when the GATE is at logic 1.

Mode 1: Hardware Retriggerable One-Shot

1. The output will be initially high.
2. When the count is loaded, and GATE is triggered, the out signal goes low. The count starts now.
3. At the end of the count (count reaches zero), the output goes high. This is like the one-shot pulse.

When the trigger input is applied again, the counter will restart counting by making the OUT signal low. In this mode, the 8253/8254 can be used as a monostable multivibrator. The waveforms for various signals in mode 1 of 8253/8254 are shown in the figure below.

Mode 2: Rate Generator

This mode functions like a divide-by-N counter.

1. The output will be initially high.
2. The output will go low for one clock pulse before the terminal count.
3. The output then goes high, the counter reloads the initial count, and the process is repeated.
4. The period from one output pulse to the next equals the number of input counts in the count register.

The count = 1 is illegal in this mode. If GATE = 1, it enables counting; otherwise, it disables counting.

Mode 3: Square Wave Generator

This mode is designed to be periodic. The output of this mode is square wave signal. The count value for this mode could be even or odd. The operation of 8253/8254 for odd and even counts is different.

Even Count

1. Initially, the output is high.
2. The counter is decremented by 2 on the falling edge of each clock pulse.
3. When the counter reaches zero, the state of output is changed (low to high or high to low).
4. The counter is reloaded with a full count, and the whole process is repeated.

Odd Count

1. Initially, the output is high.
2. The count is loaded, the first clock pulse decrements the count by 1, and subsequent clock pulses decrement the count by 2.
3. When the counter reaches zero, the state of output is changed (high to low).
4. The count is reloaded, the first clock pulse decrements the count by 3, and subsequent clock pulses decrement the count by 2.
5. When the counter is reloaded with a full count, the whole process is repeated.

Various waveforms for mode 3 of 8253/8254 are shown in the figure below.

Note: if the count (N) is even, N/2 clock pulses provide the upper half of the square wave, and N/2 clock pulses provide the lower half. Whereas if the count (N) is odd, the wave stays high for (N + 1)/2 clock pulses and stays low for (N – 1)/2 clock pulses.

Mode 4: Software Triggered Strobe

1. The output is initially low.
2. At the end of the count, the output goes low for one clock pulse.

This mode is similar to mode 2, but it is not periodic. The count is not automatically reloaded; it must be loaded again for subsequent outputs. The waveforms for mode 4 are shown in the figure below.

Mode 5: Hardware Triggered Strobe

1. The output will be initially high.
2. The counting is triggered by the rising edge of the GATE.
3. The output will go low for one clock pulse at the end of the count.

This mode is similar to mode 4, except that it is triggered by the rising edge of the pulse at the gate.

Note: In mode 5, if another trigger pulse is applied through GATE before the counter reaches zero, the count is reloaded, and the counter will restart. This is called retriggering.

Programming the 8253/8254 (PIT)

The complete functional definition of 8253/8254 is programmed by the system software. Once the 8253/8254 is programmed, the 8253/8254 is ready to perform various tasks. Each counter of the 8253/8254 is individually programmed by writing a control word into the control word register. The 8253/8254 can be programmed to provide various types of output through write operations, or to check a counter while counting through read operations. The details of these operations are given below.

WRITE Operations

To initialize a counter, the following steps are necessary.

1. Write a control word into the control register.
2. Load the low-order byte of count in the count register.
3. Load the high-order byte of count in the count register.

With the clock and appropriate gate signal to one of the counters, the above steps start the counter and provide output according to the control word.

READ Operations

In some applications, it is required to check whether the counting is completed or not. In some cases, especially in event counters, it is necessary to read the value of the count in progress.

1. Using the OUT signal – When the count value reaches zero, and counting is ended, the OUT signal goes high. This high signal can be used to interrupt the microprocessor.
2. Simple Read – It involves reading a count after stopping the counter by controlling the GATE or CLK signal. The reading operation is performed by two read operations for a 16-bit count. The first read operation reads the low-order byte, and the second operation reads the high-order byte. If there is only an 8-bit count, then it requires one read operation.
3. Reading on the Fly – In this method, the counter is read while the count is in progress. An appropriate control word is written into the control register to latch the output latch. After that, two read operations are performed to read the 16-bit count. The first read operation reads the low-order byte, and the second operation reads the high-order byte.
4. Using Read Back Command (Available only for 8254) – The read-back command in the 8254 allows the user to read the count and the status of the counter. It allows the latching of the count and status of more than one counter at a time. The format of the command is shown in the figure below.

• D₅ : 0 = Latch count of selected counter (s)
• D₄ : 0 = Latch count of selected counter (s)
• D₃ : 1 = Select counter 2
• D₂ : 1 = Select counter 1
• D₁ : 1 = Select counter 0
• D₀ = Reserved for future expansion: must be 0.

The status of the counter(s) can be read if the STATUS bit (D₄) of the read-back command is low. The status of counter(s) is latched by writing the read back command in the control register with the STATUS bit (D4) low. The status of the counter is then accessed by a read from the counter. The figure below shows the counter status format.

• D₇: 1 = OUT pin is 1.
• D₇: 0 = OUT pin is 0.
• D₆: 1 = Null count.
• D₆: 0 = Count available for reading
• D₅ – D₄: = Specifies Read/Write operation as in the control word.
• D₃ – D₁: = Specifies the mode of the counter as in the control word.
• D₀: = 1 = Binary counter
• D₀: = 1 = BCD counter