Input Output Interfacing in Microprocessor

Input Output Interfacing in Microprocessor – Any application of a microprocessor-based system requires the transfer of data from external circuitry to the microprocessor and from the microprocessor to the external circuitry. The user can give information to the microprocessor using a keyboard and can see the results or output information from the microprocessor with the help of a display device. The transfer of data between keyboard and microprocessor, and microprocessor and display device, is called input/output data transfer or I/O data transfer. This data transfer is done with the help of input/output ports.

Input Output Structure

Input port: It is used to read data from the input device, such as a keyboard. The simplest form of the input port is a buffer. The input device is connected to the microprocessor through the buffer, as shown in the figure below. This buffer is a tri-state buffer, and its output is available only when the enable signal is active. When the microprocessor wants to read data from the input device, the control signals from the microprocessor activate the buffer by asserting the enable input of the buffer. Once the buffer is enabled, data from the input device is available on the data bus. The microprocessor reads this data by initiating a read instruction.

Output port: It is used to send the data to the output device, such as a display, from the microprocessor. The simplest form of output port is a latch. The output device is connected to the microprocessor through a latch, as shown in the figure below. When a microprocessor wants to send data to the output device, it puts the data on the data bus and activates the clock input of the latch. This latches the data from the data bus to the output of the latch and makes it available for the output device.

Input and Output Interfacing

Input and output devices are the communication channels of the microprocessor to the external world. Input/output devices are connected to the microprocessor through input/output ports. There are two ways to transfer the data: (i) parallel I/O mode and (ii) serial I/O mode. In parallel I/O mode, a group of 8 bits is transferred from the microprocessor to the external world and vice versa.

In serial I/O mode, one bit is transferred using one line only. In this chapter, we will focus on interfacing I/O devices in parallel mode only. I/O interfacing can also be classified into CPU-initiated I/O transfer and device-initiated I/O transfer. This classification of input/output interface is shown below.

1. CPU initiated
   1. Conditional
   2. Unconditional
2. Device initiated
   1. Interrupt
   2. DMA

CPU-initiated I/O transfers are again categorised into conditional and unconditional. During an unconditional CPU-initiated I/O transfer, the input/output devices are always ready to give/take data whenever the microprocessor wants to do so. Whereas during a conditional CPU-initiated I/O transfer, the input/output device communicates only if it is free.

Input/Output Interfacing Techniques

In parallel I/O mode, devices can be interfaced with the 8085 microprocessor using two techniques:

1. Peripheral-mapped I/O
2. Memory-mapped I/O

The basic process for data transfer in both techniques is similar. When a data transfer instruction is executed for an I/O device, the microprocessor places the appropriate address on the interfacing device and transfers the data.

Peripheral Mapped I/O

In peripheral mapping, the addresses assigned to memory locations can also be assigned to I/O devices. Since the same address may be assigned to a memory location or an I/O device, the microprocessor must issue a control signal to differentiate whether the address on the address bus is for a memory location or for an I/O device. In the 8085 microprocessor, IO/M signal is used for this purpose. The 8085 microprocessor outputs a logic ‘1’ on the IO/M line for an I/O operation and a logic ‘0’ for a memory operation. In peripheral mapped I/O, a device is identified with an 8-bit address and a control signal IO/M = 1.

The 8085 microprocessor uses a 16-bit wide address bus for addressing memories and I/O devices. In peripheral mapped I/O interfacing out of 16 lines of address bus, 8 lines are used for memory locations and 8 lines for I/O devices. Therefore, in this interfacing, we can have 256 (2⁸) memory locations and 256 (2⁸) I/O devices. The address for both ranges from 00H to FFH. This is shown in the figure below.

Since the address of any device or memory location is 8-bit, the same address will be copied to the higher-order address bus (A₈ – A₁₅) and lower-order address bus (A₀ – A₇). For example, if the address of a device is 60H, then the content of the higher order address bus (A₈ – A₁₅) as well as of the lower order address bus (A₀ – A₇) will be 60H.

Memory-Mapped I/O

In memory-mapped I/O, there is only one address space. In this, a device is identified by a 16-bit address and enabled by a memory-related control signal. Since the 8085 microprocessor uses a 16-bit wide address bus, it can access 2¹⁶ = 64K bytes of memory and I/O devices. Some addresses are assigned to memory locations, and some addresses to I/O devices. In this interfacing, a memory location and an I/O device can not have the same address. Suppose that memory locations are assigned the addresses from 7000H to 73FFH. One address is assigned to each memory location. Any one of these addresses can not be assigned to an I/O device. The addresses for I/O devices are different from the addresses that have been assigned to memory locations. Hence, an I/O device can also be treated as a memory location. A block diagram for memory-mapped I/O is shown below.

Comparison Between Memory Mapped I/O and Peripheral Mapped I/O

Memory Mapped I/O	Peripheral Mapped I/O
In this, the device address is 16 bits. (A0 – A15) Address lines are used to generate the device address.	In this, the I/O device address is 8 bits. (A0 – A7) or (A8 – A15) lines are used to generate the device address.
The control signal IO/M = 1	The control signal IO/M = 1
Data transfer is between any register and an I/O device.	The maximum number of I/O devices is 256.
The maximum number of I/O devices is 216 (65,536) if no memory location is connected.	The maximum number of I/O devices is 256.
Decoding a 16-bit address may require more hardware.	Decoding an 8-bit address will require less hardware.
The number of instructions is available for data communication.	Only two instructions (IN and OUT) are available for data communication.
Arithmetic and logic operations can be directly performed with I/O data.	Not available.

Note: Instructions available to communicate data between the microprocessor and peripheral are separate for memory-mapped I/O and peripheral-mapped I/O.

Input/Output Device Selection

When input/output devices are interfaced to the 8085 microprocessor with the peripheral mapped I/O technique, the microprocessor generates an 8-bit I/O address. This means it can select one of the 2⁸ = 256 I/O ports. To choose the desired I/O device, the following steps must be followed:

1. Decode the address to generate a unique signal corresponding to the device address on the bus. This is named the device address signal.
2. When the device address signal and control signal (IOR or IOW) are low, generate the device select signal. The control signal IOR, which is a logical combination of IO/M and RD control signals, is low. In the same manner, IOW, which is a logical combination of IO/M and WR. goes low if both IO/M and WR control signals are low.
3. Use the device select signal to activate the interfacing device or I/O port.

The figure below shows the absolute decoding circuit for the I/O device. A 3: 8 decoder is used to generate the device address signal (O₀). This is ORed with the control signal (IOR or IOW) to generate the device select signal.

To activate the decoder IC, G₁ and G₂ must be low, whereas G₃ must be high. It means A₇ = I. A₆A₅A₄ = 0 and A₃ = 0. To generate a device select signal (O₀) low, A₂A₁A₀ = 000. Therefore, the address of the selected device is as follows.

A7 A6 A5 A4 A3 A2 A1 A0
1  0  0  0  0  0  0  0 => 80H

This shows that the address on the address bus must be 80 H to select the I/O device connected to the buffer in the above figure. The same concept may be applied to select a device connected in a memory-mapped I/O technique. The difference is in the number of address lines (16 instead of 8) and the control signal (IO/M instead of IO/M = 1).

Interfacing Input Device

The microprocessor 8085 accepts 8-bit data from the input devices. The input device could be a keyboard, a sensor, a transducer, etc.

The input device is interfaced with the 8085 microprocessor with the help of the input port. In most of the cases, a tri-state buffer is used as an input port. An example of input device interfacing is shown in the above figure. A tri-state buffer is used as the input port for 8 DIP switches. The same decoder circuit is used for device selection. The address for this input device is 80H as discussed earlier. When 80H is transferred to the address bus by the 8085 microprocessor, the input port (tri-state buffer) is activated, and the status of the DIP switches moves to the data bus. From the data bus, the microprocessor accepts the information.

The figure below shows a schematic of an interfacing I/O device using memory mapped I/O. The circuit includes one input port with eight DIP switches. A 3-to-8 decoder circuit is used to decode the sixteen address lines.

To activate the decoder, G₁ and G₂ must be low, whereas G₃ must be high. It means A₁₅ = 1, A₁₂A₁₁A₁₀A₉A₈ = 00000 and A₇A₆A₅A₄A₃ = 00000.

To generate O₀, signal low, A₂A₁A₀ = 0. The two address lines (A₁₃ and A₁₄) of the 8085 microprocessor are not used for decoding the address, hence A₁₄A₁₃ (don’t care). The address lines A₁₄ and A₁₃ may have four values (00, 01, 10, and 11). The device has four addresses as follows:

A15	A14	A13	A12	A11	A10	A9	A8	A7	A6	A5	A4	A3	A2	A1	A0	Address
1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	8000H
1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	A000H
1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	C000H
1	1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	E000H

Therefore, the selected device has four addresses: 8000H, A000H, C000H, and E000H. This is called partial/linear decoding.

Interfacing Output Device

The microprocessor 8085 sends 8-bit data to the output device, such as a seven-segment display. LEDs, printers, etc. The output port is used to interface the 8085 microprocessor with an output device. Latch is used as the output port. Although the information or data coming from the microprocessor to the output device is available on the data bus for a few microseconds, it can be stored in the latch with the help of an appropriate control signal.

The figure below shows the circuit diagram to interface the output port latch, which is used to send the signal to glow the LEDs. The LED will glow when the output pin status is low. The figure below shows a practical decoding circuit for the output device with the address 81H.

The decoder and three-input OR gate are used to generate the device address signal (Y₁). When the address bus carries address 81H, the device select signal is a low signal; otherwise, it is high. The device address signal (Y) combines with the control signal IOW to generate the device select signal when both input signals are low. Meanwhile, the contents of the accumulator are placed on the data bus and are available on the data bus for a few microseconds, and therefore, must be latched for LEDs. The device select signal stores the data into the latch for display by the LEDs.

Note: As an interfacing device, a latch is used for an output port, and a tri-state buffer is used for an input port.